<i>RC</i> Benefits of Advanced Metallization Options

Ciofi, Ivan; Roussel, Philippe; Baert, Rogier; Contino, Antonino; Gupta, Anshul; Croes, Kristof; Wilson, Christopher J.; Mocuta, D.; Tőkei, Zsolt

doi:10.1109/ted.2019.2902031

Cited by 42 publications

(18 citation statements)

References 22 publications

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“…The distance between the top/bottom surface of the evaluated interconnect to the power/ground is set as 20 nm [H cu (in Fig. 1)], which is smaller than the nominal value of 36 nm [25]. Hence, it increases the coupling capacitance to power/ground.…”

Section: Cu and Cnt Interconnect Descriptionmentioning

confidence: 99%

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

Chen

Lin

Liang

et al. 2022

IEEE Trans. VLSI Syst.

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The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a carbon nanotube (CNT) SRAM array composed of the schematically optimized CNFET SRAM and CNT interconnects. We consider the interconnects inside the CNFET SRAM cell composed of metallic single-wall CNT (M-SWCNT) bundles to represent the metal layers 0 and 1 (M0 and M1). We investigate the layout structure of CNFET SRAM cell considering CNFET devices, M-SWCNT interconnects, and metal electrode Palladium with CNT (Pd-CNT) contacts. Two versions of cell layout designs are explored and compared in terms of performance, stability, and power efficiency. Furthermore, we implement a 16 Kbit SRAM array composed of the proposed CNFET SRAM cells, multiwall CNT (MWCNTs) inter-cell interconnects and Pd-CNT contacts. Such an array shows significant advantages, with the read and write overall energy-delay product (EDP), static power consumption, and core area of 0.28×,0.52×, and 0.76× respectively to 7-nm FinFET-SRAM array with copper interconnects, whereas the read and write static noise margins are 6% and 12% respectively larger than the FinFET counterpart.This work was supported in part by the European Commission H2020 CONNECT Project under Agreement 688612 (http://www.connect-h2020.eu/) and in part by the Marie Skłodowska-Curie Individual Fellowship under Grant 894805 (H-3D-SOC).

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Section: Cu and Cnt Interconnect Descriptionmentioning

confidence: 99%

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

Chen

Lin

Liang

et al. 2022

IEEE Trans. VLSI Syst.

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“…For example, at about 40 nm via CD, the via resistance reduction is ~ 30% [ 260 ]. By using hybrid Cu metallization with Co via-prefill, the resistance of a 12 nm half-pitch via can be lowered by up to 42% in 87° tapered vias and up to 52% in chamfered vias [ 262 ]. Therefore, selective Co process for contact and via prefill has the potential to enable future scaling of advanced technology node.…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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“…Even though reliability/performance of horizontal wires by SE process for both metals [21], [7] and DMLG [19], [20] are well studied, realization and characterization of a multi-tier graphene interconnect system by SE incorporating robust and low resistance vias/contacts have remained elusive. Vias are crucial elements for signal propagation between various metallization levels, which also suffer from significant EM at advanced technology nodes [23], as also shown in detail in Section II-B. Jiang et al [24] reported carbon nanotube (CNT) vias integrated with horizontal multi-tier multilayer graphene (MLG) wires by SE process with extremely high EM resistance in CNT vias, MLG wires, and their contacts.…”

mentioning

confidence: 99%

Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

Agashiwala

Jiang

Parto

et al. 2021

IEEE Trans. Electron Devices

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Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, selfheating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-level graphene interconnect technology (with vias) has remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on dielectric (SiO 2) and metal (Cu) substrates and subsequently demonstrating multi-level MLG interconnects with metal vias. Using rigorous theoretical and experimental analyses, we demonstrate that multi-level MLG interconnects with metal vias undergo < 2% change in the via resistance under accelerated stress conditions, demonstrating its superior reliability against SH and EM, making them ideal candidates for sub-10 nm nodes.

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RC Benefits of Advanced Metallization Options

Cited by 42 publications

References 22 publications

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

State of the Art and Future Perspectives in Advanced CMOS Technology

Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

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