2021
DOI: 10.1109/ted.2021.3061637
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Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

Abstract: Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, selfheating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-lev… Show more

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Cited by 11 publications
(4 citation statements)
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“…This RTD behavior employing graphene was theoretically proposed and demonstrated in, [ 303 ] where a Gr NDR device ( Figure a) with suitably designed width for the source/drain and the channel regions offered a suitable band‐alignment (Figure 12b) resulting in large peak‐valley current ratios (PVCR) (Figure 12c) exceeding 10 14 , essential in digital applications. Moreover, the relatively low contact resistance of metal‐Gr contacts [ 304 ] and progress on fabricating Gr nanoribbons [ 292 ] make this concept realizable in the future. A RTD fabricated on vertical MoS 2 –WSe 2 heterojunctions was reported, [ 305 ] where a room‐temperature PVCR of ≈2.2 was obtained.…”
Section: Quantum Mechanical Tunneling Devices For Logic and Memorymentioning
confidence: 99%
“…This RTD behavior employing graphene was theoretically proposed and demonstrated in, [ 303 ] where a Gr NDR device ( Figure a) with suitably designed width for the source/drain and the channel regions offered a suitable band‐alignment (Figure 12b) resulting in large peak‐valley current ratios (PVCR) (Figure 12c) exceeding 10 14 , essential in digital applications. Moreover, the relatively low contact resistance of metal‐Gr contacts [ 304 ] and progress on fabricating Gr nanoribbons [ 292 ] make this concept realizable in the future. A RTD fabricated on vertical MoS 2 –WSe 2 heterojunctions was reported, [ 305 ] where a room‐temperature PVCR of ≈2.2 was obtained.…”
Section: Quantum Mechanical Tunneling Devices For Logic and Memorymentioning
confidence: 99%
“…To fabricate multilevel MLG interconnects, low-resistance vias are required, and metal contact, such as Co, to the MLG interconnect edge is considered to be promising. 63) Furthermore, process optimization for the via-etching and cleaning will be necessary to avoid desorption of intercalates during the processes.…”
Section: Further Issues and Prospectsmentioning
confidence: 99%
“…While further scaling down the feature size, the researchers are confronting major challenges not only from the CMOS design but also due to interconnects, some of which are directly imposed due to quantum effects [11]. To solve this problem, several other technologies are being explored such as nanowires, nanotubes [12], [13], [14], [15], [16], [17], Quantum wires [18], [19], [17], [20], etc. other than metallic interconnects [21].…”
Section: Introductionmentioning
confidence: 99%