2010
DOI: 10.1117/12.849356
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Hybridization process for back-illuminated silicon Geiger-mode avalanche photodiode arrays

Abstract: Hybridization process for back-illuminated silicon Geiger-mode avalanche photodiode arrays The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation Schuette, Daniel R. et al. "Hybridization process for backilluminated silicon Geiger-mode avalanche photodiode arrays." Advanced Photon Counting Techniques IV.

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Cited by 12 publications
(8 citation statements)
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“…4 The APD wafer process includes the following sequence of steps: (1) APD substrate removal, (2) processing of the back side of the APD to form an ion implanted p+ contact layer, sparse back-side contact metallization, and antireflection coating, (3) transfer of the APD to a fused silica substrate, and (4) front side processing leading to patterning of indium bumps on the APD arrays. Steps 1 through 3 are carried out with the APD wafer fusion bonded on the front side to a temporary silicon handle wafer, which is then removed by grinding and etch prior to step 4.…”
Section: Apd Fabrication and Integration With Cmos Readoutmentioning
confidence: 99%
“…4 The APD wafer process includes the following sequence of steps: (1) APD substrate removal, (2) processing of the back side of the APD to form an ion implanted p+ contact layer, sparse back-side contact metallization, and antireflection coating, (3) transfer of the APD to a fused silica substrate, and (4) front side processing leading to patterning of indium bumps on the APD arrays. Steps 1 through 3 are carried out with the APD wafer fusion bonded on the front side to a temporary silicon handle wafer, which is then removed by grinding and etch prior to step 4.…”
Section: Apd Fabrication and Integration With Cmos Readoutmentioning
confidence: 99%
“…This processing step creates a thin mesa of detector material as illustrated in Figure 2. Alternatively, a UV transparent substrate may be attached to the detector wafer and the initial silicon wafer removed, as described in [6], to form a bump-bondable array. …”
Section: Uvapd Fabrication Processmentioning
confidence: 99%
“…This process fabricates APD arrays that may be vertically integrated with CMOS support electronics via techniques including flip-chip bump bonding ( [6]) or 3D circuit integration ( [7]), facilitating high-density detector integration for compact devices. The UVAPD front illumination steps follow our standard process flow, outlined in [6]. It begins with a series of implants that form the active region of the device, followed by interconnecting metals and a capping oxide.…”
Section: Uvapd Fabrication Processmentioning
confidence: 99%
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“…Another application is chronic biomedical monitoring [9], where a wearable or implantable miniaturized single-photon sensor could be left in situ to continuously monitor a person's health status, providing more accurate information about the progression of diseases such as cancer and other inflammatory or chronic ailments. However, current SPAD technology is generally implemented on bulk silicon and can't meet the requirements of implantable biomedical applications where backside-illumination and new substrate post processing are core technologies, while inherent CMOS compatibility is a requirement [10,11]. In our previous work, we demonstrated the world's first flexible SPAD fabricated in an ultrathin-body silicon-on-insulator (SOI) process followed by transfer post-processing to flexible substrate [12], and we achieved a flexible SPAD with dual-side illumination for the first time [13].…”
Section: Introductionmentioning
confidence: 99%