Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

Fenouillet-Béranger, C.; Perreau, P.; Pham-Nguyen, Loan; Denorme, S.; Andrieu, F.; Tosti, L.; Brévard, L.; Weber, O.; Barnola, S.; Salvetat, T.; Garros, X.; Cassé, M.; Leroux, C.; Noël, J.‐P.; Thomas, Olivier; Le-Gratiet, Bertrand; Baron, F. A.; Gatefait, Maxime; Campidelli, Y.; Abbate, F.; Perrot, C.; De-Buttet, C.; Beneyton, R.; Pinzelli, L.; Leverd, F.; Gouraud, P.; Gros-Jean, M.; Bajolet, A.; Mezzomo, Cecilia M.; Leyris, C.; Haendler, S.; Noblet, D.; Pantel, R.; Margain, A.; Borowiak, C.; Josse, E.; Planes, N.; Delprat, D.; Boedt, F.; Bourdelle, K.K.; Nguyen, Bich‐Yen; Bœuf, F.; Faynot, O.; Skotnicki, T.

doi:10.1109/iedm.2009.5424251

Cited by 41 publications

(27 citation statements)

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“…In the case of 122 SRAM cell, both PFET and NFET mask can be shared with HVT logic device VT mask to reduce the cost of the technology; thereby selecting 122 as technology SRAM cell will reduce cost of the technology at highest performance and desired yield. In [18], [20], and [21], SRAM devices are targeted at 30 pA/um I off , which is in close proximity of I off achieved by 122 SRAM cell devices as seen in Fig. 13.…”

Section: Determination Of Technology Hd Sram Cellmentioning

confidence: 97%

“…9). Maximum μ Iread /μ leak of 0.33 × 10 6 for In published FinFET [20], [21] and FDSOI [18] technologies, SRAM devices are targeting 30 pA/um OFF current (I off ) at nominal supply voltage. It is explicitly mentioned that logic high threshold voltage (HVT) transistor of FinFET technology have same device as SRAM device [20], [21], similar to SOI technology [18], where HVT transistors are used for designing SRAM cell with larger Lg.…”

Section: Determination Of Technology Hd Sram Cellmentioning

confidence: 99%

“…Maximum μ Iread /μ leak of 0.33 × 10 6 for In published FinFET [20], [21] and FDSOI [18] technologies, SRAM devices are targeting 30 pA/um OFF current (I off ) at nominal supply voltage. It is explicitly mentioned that logic high threshold voltage (HVT) transistor of FinFET technology have same device as SRAM device [20], [21], similar to SOI technology [18], where HVT transistors are used for designing SRAM cell with larger Lg. For reported VTs for SRAM devices in Table VI at Lg = 24 nm, If 112 is selected as technology HD SRAM cell, then NFET VT mask can be shared with logic HVT device to reduce the cost of the technology, but PFET VT mask cannot be shared because an additional HVT PFET mask for WF tuning is required for logic device as shown in Fig.…”

Section: Determination Of Technology Hd Sram Cellmentioning

confidence: 99%

“…As SADP uses single lithography and etching step, it has minimum overlay issue between two neighboring gates, ensures uniform source and drain contact space, and reduces pattern variability. It is a wellknown practice to have larger Lg for SRAM devices in CMOS technologies [18], [20], [21]. Increasing Lg reduces effective contact space and thus increases contact resistance of device, but reduces leakage and device variability [3].…”

Section: B Target Read Current Estimationmentioning

confidence: 99%

See 3 more Smart Citations

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Sakhare

Miyaguchi

Raghavan

et al. 2015

IEEE Trans. Electron Devices

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For the first time, we present complete device threshold voltage (VT)-targeting methodology for FinFET SRAM in 10-nm technology, considering capacitance due to metal pattering and device variability to set target read current for different variants of SRAM architecture to determine technology highdensity (HD) SRAM cell. The VT-targeting methodology brings into play the worst case read and write margins available for SRAM cell to determine nominal device VT by tuning the work function of metal gate. Analysis shows that for minimum leakage current, 112 SRAM cell is optimum, whereas for the same area of 0.0546 μm 2 with 50% higher leakage, 122 SRAM outperform by 5% and 20% improved read and write margins, respectively. The 122 SRAM as HD cell reduces the cost of the technology by sharing P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) VT mask with the high threshold voltage logic devices, whereas the 112 SRAM device shares only NFET VT mask. The 111 SRAM can achieve target performance at lesser area of 0.048 μm 2 by compromising read stability, which will result in lower yield. At 64-nm pitch, litho-etch litho-etch (LELE) double-patterned gate impacts device performance and alleviates variability; hence the read margin of SRAM cell should consider an additional 1σ rsnm margin to retain the same yield in 10-nm-technology era.Index Terms-10-nm technology, design methodology, design technology co-optimization (DTCO), double patterning gate, FinFET SRAM design, high density (HD), selfaligned double patterning (SADP), self-aligned quadruple patterning (SAQP), SRAM threshold voltage (VT) targeting, technology SRAM.

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Section: Determination Of Technology Hd Sram Cellmentioning

confidence: 97%

Section: Determination Of Technology Hd Sram Cellmentioning

confidence: 99%

Section: Determination Of Technology Hd Sram Cellmentioning

confidence: 99%

Section: B Target Read Current Estimationmentioning

confidence: 99%

See 2 more Smart Citations

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Sakhare

Miyaguchi

Raghavan

et al. 2015

IEEE Trans. Electron Devices

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“…5,6 UTB structure also offers great compatibility with mainstream planar CMOS for high density integration. 7,8 The performance of these FD-SOI devices are inevitably influenced by the interface traps of buried oxide, in addition to those of the front oxide, as they would degrade the sub-threshold swing, transconductance and device uniformity as the film thicknesses are scaled down. 9 Thus, a simple and reliable approach for D it extraction for both the front and back interfaces simultaneously is highly desired.…”

mentioning

confidence: 99%

Extraction of Front and Buried Oxide Interface Trap Densities in Fully Depleted Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor

Cheng

Yeung

2013

ECS Solid State Letters

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In this letter, a method is proposed and demonstrated for the first time to characterize and decouple the interface traps of both the frontand back channels of fully-depleted silicon-on-insulator (FD-SOI) metal-oxide-semiconductor field-effect transistor (MOSFET). We report the procedure and the underlying theory that allows the extraction of the energy profiles of the densities of the interface traps (D it ).This technique will be very useful for evaluating the interface qualities of future FD-SOI transistors.The fully-depleted silicon on insulator (FD-SOI) ultra-thin body UTBSOI MOSFET 1-3 is gaining new attention as an alternative technology to FinFET 4 for ultra-low power and mobile applications because of its outstanding electrostatics, low device variability due to excellent suppression of the short channel effect (SCE) with undoped channel and ultra-thin body. 5,6 UTB structure also offers great compatibility with mainstream planar CMOS for high density integration. 7,8 The performance of these FD-SOI devices are inevitably influenced by the interface traps of buried oxide, in addition to those of the front oxide, as they would degrade the sub-threshold swing, transconductance and device uniformity as the film thicknesses are scaled down. 9 Thus, a simple and reliable approach for D it extraction for both the front and back interfaces simultaneously is highly desired. The most commonly used technique for characterizing the D it , i.e., the charge pumping (CP) method, requires a body contact and/or with additional optical assistance as well as a gated-diode-like device 10-13 to supply the majority carrier, cannot be applied to future FD-SOI technologies as they do not provide body contacts. Nevertheless, conductance method only reflects mixing result of front-and back density of interface state instead of their individual contribution. Besides, conventional capacitance-voltage (C-V) method 14,15 is not appropriate for FD-SOI nowadays because of the large gate leakage current at low frequencies and the high series resistance at high frequencies. Therefore, DC current-voltage based technique is the most attractive. One may apply the sub-threshold technique by accumulating one channel while sweeping the gate bias of the opposite channel to evaluate the D it , and it works well for a relatively thick film. 16 However, for the very thin silicon film thicknesses, it is not possible to accumulate one channel while inverting the opposite channel without using high voltages that would damage the thin gate oxide due to the strong capacitive coupling of the two channels. 17 The back surface potential will always follow the front gate voltage, i.e., the volume inversion occurs. Therefore, a dual-gate (DG) voltage-sweep technique has been utilized to characterize the buried density of interface traps (D itB ) for FD-SOI involving sweeping both channels in sub-threshold region, thus an average back channel D itB can be derived by neglecting the D itF . 18 However, ignoring the D itF introduces unknown errors and an avera...

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Logic Devices Challenges and Opportunities in the Nano Era

Bœuf

2017

Nanoelectronics

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Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

Cited by 41 publications

References 1 publication

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Extraction of Front and Buried Oxide Interface Trap Densities in Fully Depleted Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor

Logic Devices Challenges and Opportunities in the Nano Era

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