In this letter, a method is proposed and demonstrated for the first time to characterize and decouple the interface traps of both the frontand back channels of fully-depleted silicon-on-insulator (FD-SOI) metal-oxide-semiconductor field-effect transistor (MOSFET). We report the procedure and the underlying theory that allows the extraction of the energy profiles of the densities of the interface traps (D it ).This technique will be very useful for evaluating the interface qualities of future FD-SOI transistors.The fully-depleted silicon on insulator (FD-SOI) ultra-thin body UTBSOI MOSFET 1-3 is gaining new attention as an alternative technology to FinFET 4 for ultra-low power and mobile applications because of its outstanding electrostatics, low device variability due to excellent suppression of the short channel effect (SCE) with undoped channel and ultra-thin body. 5,6 UTB structure also offers great compatibility with mainstream planar CMOS for high density integration. 7,8 The performance of these FD-SOI devices are inevitably influenced by the interface traps of buried oxide, in addition to those of the front oxide, as they would degrade the sub-threshold swing, transconductance and device uniformity as the film thicknesses are scaled down. 9 Thus, a simple and reliable approach for D it extraction for both the front and back interfaces simultaneously is highly desired. The most commonly used technique for characterizing the D it , i.e., the charge pumping (CP) method, requires a body contact and/or with additional optical assistance as well as a gated-diode-like device 10-13 to supply the majority carrier, cannot be applied to future FD-SOI technologies as they do not provide body contacts. Nevertheless, conductance method only reflects mixing result of front-and back density of interface state instead of their individual contribution. Besides, conventional capacitance-voltage (C-V) method 14,15 is not appropriate for FD-SOI nowadays because of the large gate leakage current at low frequencies and the high series resistance at high frequencies. Therefore, DC current-voltage based technique is the most attractive. One may apply the sub-threshold technique by accumulating one channel while sweeping the gate bias of the opposite channel to evaluate the D it , and it works well for a relatively thick film. 16 However, for the very thin silicon film thicknesses, it is not possible to accumulate one channel while inverting the opposite channel without using high voltages that would damage the thin gate oxide due to the strong capacitive coupling of the two channels. 17 The back surface potential will always follow the front gate voltage, i.e., the volume inversion occurs. Therefore, a dual-gate (DG) voltage-sweep technique has been utilized to characterize the buried density of interface traps (D itB ) for FD-SOI involving sweeping both channels in sub-threshold region, thus an average back channel D itB can be derived by neglecting the D itF . 18 However, ignoring the D itF introduces unknown errors and an avera...
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