We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 10 10 cycles. The ferroelectric transistors (FeFETs) incorporate a high-κ interfacial layer (IL) of thermally grown silicon nitride (SiN x ) and a thin 4.5 nm layer of Zr-doped FE-HfO 2 (HZO) on a ∼30 nm silicon on insulator (SOI) channel. The device shows a ∼1V memory window (MW) in a DC sweep of just ± 2.5V, and can be programmed and erased with voltage pulses of V G = ± 3V at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.