Modeling and characterization of gate oxide reliability

“…The main experimental evidence in support of this was a constant value of the hole fluence to breakdown as a function of oxide field [60] C/cm , where the injected hole flux is obtained from the substrate hole current using n-FETs biased in inversion, although it was later shown that decreases for less than about 6 nm [61] and that the constancy of does not hold at temperatures below 300 K [65]. The AHI model is commonly associated with a time-to-breakdown dependence on oxide field of the form -constant (referred to as the " model") [66], but since this dependence comes mostly from the form of the Fowler-Nordheim current it is not an essential element of the physical model and would not be expected to hold in the direct tunneling regime [67].…”

Section: Physical Models For Defect Generationmentioning

confidence: 99%

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

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“…Reliability in this case is measured by the presence of defects or holes in the metallization layer. 46 Surface roughness data reporting is also greatly expanded, and the entire set of measurement data is repeated to analyze and compare the results of a tinned vs. untinned seed layer. Along with providing additional data, the equipment and techniques used to gather the measurement data have been modified from the first study.…”

Section: B3068mentioning

confidence: 99%

A Low-Cost, Micropattern Transfer Process for Thick-Film Metallization of PDMS

Hilbich

Gray

Shannon

2017

J. Electrochem. Soc.

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We present the detailed characterization of a novel microfabrication process to produce thick-film copper microstructures that are embedded in polydimethylsiloxane (PDMS). This process has reduced fabrication complexity and cost compared to existing metal-on-PDMS techniques and enables rapid prototyping of designs using minimal microfabrication equipment. This technology differs from others in its use of a conductive copper paint seed layer and a unique infrared-assisted transfer process that results in copper microstructures embedded in PDMS. By embedding microstructures flush with the PDMS surface, rather than fabricating the microstructures on the substrate surface, we produce a metallization layer that adheres to PDMS without the need for surface modifications. In addition, the electrodeposition process results in a highly-conductive, thick-film, copper layer. Deposited patterns are shown to be 70-micrometers-thick with reliable feature sizes as small as 100 micrometers. The copper layer has a surface roughness of approximately 5 micrometers and a low film resistivity of approximately 2.5-3 micro--cm.

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Modeling and characterization of gate oxide reliability

Cited by 358 publications

References 23 publications

Dielectric breakdown I: A review of oxide breakdown

Dielectric breakdown I: A review of oxide breakdown

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

A Low-Cost, Micropattern Transfer Process for Thick-Film Metallization of PDMS

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