Hot Carrier Degradation-Induced Dynamic Variability in FinFETs: Experiments and Modeling

Yu, Zhuoqing; Sun, Zixuan; Wang, Runsheng; Zhang, Jiayang; Huang, Ru

doi:10.1109/ted.2020.2974864

Cited by 25 publications

(9 citation statements)

References 28 publications

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“…While the BTI generates the electrical field perpendicular to the channel, the hot carrier injection (HCI) combines horizontal and perpendicular electric field to the channel. The HCI accompanied with the self-heating effect exhibits more degradation for FinFETs than what is expected [25][26][27]. However, the interface state generation and oxide trap can be passivated (recovered) by bond formation with hydrogen atoms [26,28].…”

Section: Introductionmentioning

confidence: 94%

“…The HCI accompanied with the self-heating effect exhibits more degradation for FinFETs than what is expected [25][26][27]. However, the interface state generation and oxide trap can be passivated (recovered) by bond formation with hydrogen atoms [26,28]. HCI is also a critical factor to shift V t in compared with other reliability mechanisms [24].…”

Section: Introductionmentioning

confidence: 94%

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Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Chang¹,

Li²,

Hsu³

et al. 2021

IEEE Open J. Nanotechnol.

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High-k metal gate technology improves the performance and reduces the gate leakage current of metal-oxide-semiconductor field-effect transistors (MOSFETs). This study investigated four different work function metal (WFM) stacks in the gate of fin field-effect transistors (FinFETs) on the same substrate. These devices not only successfully produced distinct levels of threshold voltages (|V t |) but also converted n-to p-type features merely by adding p-type WFM in the gate of the MOSFETs. All of the devices satisfied short-channel effects with shrinking channel length. The gate-to-body electric field induced drain leakage due to the nature of bulk FinFETs. However, the n-and p-type gate stacks presented different gate current leakage. For reliability, hot carrier injection (HCI) could have a higher reliability impact than the negative-bias temperature instability (NBTI) for p-MOSFET, although the stress voltage of HCI was roughly half that of the NBTI test. This multi-threshold voltage tuning allows designers to design CMOS and choose the trade-off between low power consumption and high performance on the same platform.

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Section: Introductionmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 94%

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Chang¹,

Li²,

Hsu³

et al. 2021

IEEE Open J. Nanotechnol.

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“…From the trap-based research in HCD, both interface and oxide traps contribute to the overall degradation [ 5 ]. A modified compact model and trap spatial distribution investigations facilitate the accurate characterization of HCD [ 6 , 7 , 8 ]. To characterize the trap generation during HCD stress, a discharge-based multi-pulse technique (DMP) was introduced, which is accessible to oxide traps within and beyond the bandgap [ 9 , 10 ].…”

Section: Introductionmentioning

confidence: 99%

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

Chang

Wang²,

Yang

et al. 2023

Nanomaterials

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In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (−2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.

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“…When flowing through the conduction channel, these hot electrons collide with the host lattice and transfer energies to the latter inevitably. It makes a transistor continuously give off heat to the environment and accounts for the heat-dissipation constraints of chips [ 2 , 3 ]. Similarly, hot carriers in solar cells were commonly considered to cause great loss (∼42%) of efficiency [ 4–6 ], because these hot carriers, typically generated by absorbing high-energy photons (above the bandgap of the semiconductor), tend to dissipate excess energies through the relaxation process [ 7 , 8 ].…”

Section: Introductionmentioning

confidence: 99%

Direct observation and manipulation of hot electrons at room temperature

Wang

Xia

et al. 2020

National Science Review

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In modern electronics and optoelectronics, hot electron behaviors are highly concerned since they determine the performance limit of a device or system, like the associated thermal or power constraint of chips, the Shockley-Queisser limit for solar cell efficiency. Up-to-date, however, the manipulation of hot electrons is mostly based on conceptual interpretations rather than a direct observation. The problem arises from a fundamental fact that energy-differential electrons are mixed up in real-space, making it hard to distinguish them from each other by standard measurements. Here we demonstrate a distinct approach to artificially (spatially) separate hot electrons from cold ones in semiconductor nanowire transistors, which thus offers a unique opportunity to observe and modulate electron occupied state, energy, mobility, and even its path. Such a process is accomplished through the scanning-photocurrent-microscopy (SPCM) measurements by activating the intervalley-scattering events and one-dimensional charge-neutrality rule. Findings discovered here may provide a new degree of freedom in manipulating nonequilibrium electrons for both electronic and optoelectronic applications.

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Hot Carrier Degradation-Induced Dynamic Variability in FinFETs: Experiments and Modeling

Cited by 25 publications

References 28 publications

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

Direct observation and manipulation of hot electrons at room temperature

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