Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for Monolithic 3-D Integration of InGaAs MOSFETs

Abstract

Self-heating has emerged as an important performance/reliability challenge for modern MOSFETs. The challenge is further acerbated for III-V transistors, especially when integrated monolithically in a 3-D platform for applications in ultrafast logic, imagers, etc. A key challenge is the difficulty of heat-dissipation through the ultra-thin channels needed to ensure electrostatic integrity of scaled transistors. In this paper, we demonstrate an innovative use of a heat-dissipating shunt of Ni-InGaAs on InGaAs(111) in the S/D extension region, as well as the use of high-conductivity Mo contact to simultaneously improve electrical and thermal stability and heat dissipation in III-V transistors, such that the peak channel temperature is reduced by as much as 25%-30%. Given the exponential temperature sensitivity of transistor reliability, heat shunts will improve transistor lifetime significantly.

Accurate evaluation of specific contact resistivity between InAs/Ni–InAs alloy using a multi-sidewall transmission line method

“…24) Also, Ni-InAs was used for the S/D metal. Here, since Ni-InGaAs formed on (111) InGaAs is thermally more stable than Ni-InGaAs formed on (100) InGaAs, 5) similar stability characteristics are expected for Ni-InAs. The flow of the fabrication process is shown in Fig.…”

“…1,2) Conventional ion implantation techniques are not easy to apply to 3D CMOS devices because of the high annealing temperature needed for dopant activation. In contrast, metal source/drain (S/D) structures, formed by an implantation-free process at low temperature, can be used for the S/D of InGaAs [3][4][5][6] and InAs [6][7][8] n-channel MOS field effect transistors (n-MOSFETs). Metal-In(Ga)As alloys such as Ni-InGaAs and Ni-InAs can be used to realize an ultra-shallow, steep junction by control of the initial metal thickness, providing a promising approach for 3D CMOS devices.…”

“…The reported contact resistivity, ρ int , between Ni-InGaAs and InGaAs (doping concentration, N D = 5.7 × 10 19 cm −3 ) is 2.0 × 10 −7 Ω cm 2 , which is still high for future CMOS technology nodes because of the non-zero Schottky barrier height (SBH). 5) On the other hand, ρ int between InAs and Ni-InAs is expected to be very low because no SBH is suggested at metal/InAs interfaces. 9) However, there have been no reports on experimental evaluation of ρ int between InAs and Ni-InAs.…”

Design of Cylindrical Surrounding Double-Gate MOSFET With Fabrication Steps Using a Layer-by-Layer Approach

“…By altering the parameters for the VLS growth process, the periodic structures can be designed over cross-sectional dimensions and the period of growth. The sawtooth morphological growth can be observed in the SNW designed using the novel atomic force microscopy (AFM) method concerning bulk [12,17].…”

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

“…Compared to the conventional standard process, low-temperature processes using approximately 650 °C have been developed, improving the performance of M3DI [ 11 , 12 , 13 ]. Currently, most M3DI devices have been researched based on metal-oxide-semiconductor field-effect transistors (MOSFETs) that use Si, Ge, and III-V materials [ 14 , 15 , 16 , 17 ]. For the majority of MOSFETs, a thermal budget is required for dopant activation after the implantation process; however, there are physical limitations for using these as low-power devices.…”