Highly scalable network on chip for reconfigurable systems

Bartic, T. Andrei; Mignolet, J.-Y.; Nollet, V.; Marescaux, Théodore; Verkest, D.; Vernalde, Serge; Lauwereins, Rudy

doi:10.1109/issoc.2003.1267722

Cited by 47 publications

(23 citation statements)

References 3 publications

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“…However, both area and frequency vary a lot: from 3 kilogates to 480 kilogates and from 1 MHz to 500 MHz. Router [26] supports variable number of ports and results are given for router with 5 input and 5 output ports. Note also, that those results are for Xilinx Virtex FPGA (embedded buffer memories are included in gate count) whereas all other results are for ASIC technologies.…”

Section: Synthesis Resultsmentioning

confidence: 99%

“…Therefore, the latency is not affected notably. However, for the configurations resulting in higher latencies (configurations [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27], the high priority offers great benefit. Regarding all configurations, high relative priority obtains 31% lower average latency and 41% lower maximum latency than the low priority.…”

Section: The Effect Of Network Parametersmentioning

confidence: 99%

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HIBI Communication Network for System-on-Chip

Salminen

Kangas

Hämäläinen

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates. HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μm technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals. Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration.

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Section: Synthesis Resultsmentioning

confidence: 99%

Section: The Effect Of Network Parametersmentioning

confidence: 99%

HIBI Communication Network for System-on-Chip

Salminen

Kangas

Hämäläinen

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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show abstract

“…Peak(1) in Figure 5 has been obtained by applying a window spreading technique ( Figure 3(b,c)) whereas the second peak was obtained by allocating continuous blocks of bandwidth (Figure 3a). In both cases the window size gradually decreases from 100% (98.85 MB/s when clocked at 50 MHz [4]) down to 0.0244% (approximately 25 KB/s). The window spreading technique clearly performs better: the throughput of the video decoder application only starts to decrease when the OS diminishes its effective window to less than 2% of the total bandwidth and reaches half of the throughput for a total allocated window of less than 1.5% (about 1.5 MB/s).…”

Section: Application Descriptionmentioning

confidence: 94%

“…Consequently, this message is sent to the slave node (2) . Once the message is received on the slave node (3) , its function number and parameters are unwrapped and the respective local OS function executes at the slave node (4) . The return value (5) is packed into a message (6) , sent over the control network to the cNIC stub, where it is unpacked (7) .…”

Section: Operating Systemmentioning

confidence: 99%

Operating-system controlled network on chip

Nollet

Marescaux

Verkest

et al. 2004

Proceedings of the 41st Annual Design Automation Conference

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Managing a Network-on-Chip (NoC) in an efficient way is a challenging task. To succeed, the operating system (OS) needs to be tuned to the capabilities and the needs of the NoC. Only by creating a tight interaction can we combine the necessary flexibility with the required efficiency. This paper illustrates such an interaction by detailing the management of communication resources in a system containing a packet-switched NoC and a closely integrated OS. Our NoC system is emulated by linking an FPGA to a PDA. We show that, with the right NoC support, the OS is able to optimize communication resource usage. Additionally, the OS is able to diminish or remove the interference between independent applications sharing a common NoC communication resource.

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“…The work by Bartic et al [2] proposes a parameterized router with varying numbers of input and output ports. Although it is similar to our configurable router, their solution left the network configuration and routing algorithm for the user to program, providing versatility at the expense of increased development time.…”

Section: Related Workmentioning

confidence: 99%

High-level specification and logic implementation of single-chip multiprocessor systems based on a configurable router

Pau

Manjikian

2008

2008 Canadian Conference on Electrical and Computer Engineering

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This paper describes prototype implementations of single-chip multiprocessor systems with a configurable router intended for dedicated, embedded network-on-chip support within fieldprogrammable gate arrays in order to provide performance and flexibility for system-on-chip applications. The router supports ring, octagon, and mesh network topologies. Implementation in an Altera Stratix EP1S80 chip is supported with a tool chain that combines custom high-level system specification software with commercial Altera software to generate single-chip multiprocessors using multiple instances of the configurable router and the Altera Nios II soft processor. A 16-node multiprocessor using a mesh topology occupies up to two-thirds of an Altera Stratix EP1S80 chip, and the aggregate communication bandwidth for a mesh is experimentally shown to be at least 11.5 Gbytes/sec with an 80-MHz system clock and 64-bit-wide connections.

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Highly scalable network on chip for reconfigurable systems

Cited by 47 publications

References 3 publications

HIBI Communication Network for System-on-Chip

HIBI Communication Network for System-on-Chip

Operating-system controlled network on chip

High-level specification and logic implementation of single-chip multiprocessor systems based on a configurable router

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