High-level specification and logic implementation of single-chip multiprocessor systems based on a configurable router

Abstract

This paper describes prototype implementations of single-chip multiprocessor systems with a configurable router intended for dedicated, embedded network-on-chip support within fieldprogrammable gate arrays in order to provide performance and flexibility for system-on-chip applications. The router supports ring, octagon, and mesh network topologies. Implementation in an Altera Stratix EP1S80 chip is supported with a tool chain that combines custom high-level system specification software with commercial Altera software to generate single-chip multiprocessors using multiple instances of the configurable router and the Altera Nios II soft processor. A 16-node multiprocessor using a mesh topology occupies up to two-thirds of an Altera Stratix EP1S80 chip, and the aggregate communication bandwidth for a mesh is experimentally shown to be at least 11.5 Gbytes/sec with an 80-MHz system clock and 64-bit-wide connections.

Design of Priority Based Reconfigurable Router in Network on Chip

“…Router architectures have dominated the early NoC researches [9] and the first NoC design proposed the use of simplistic routers with deterministic routing algorithms in terms of RTL design. Since, the router [10] is a component that is to be used in every future versions of the system, its architecture options may be either revised or coexist in the same architecture (heterogeneous NoCs [11]), it should be designed as a reusable IP block [12].…”