HIBI Communication Network for System-on-Chip

Abstract

This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates. HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μm technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals. Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration.

Evaluating SoC Network Performance in MPEG-4 Encoder

“…Single bus has often longer runtime compared to mesh [19][20][21][22] or hierarchical bus [9]. However, both single and hierarchical buses require smaller area than mesh.…”

“…The MPSoC uses Heterogeneous IP Block Interconnection (HIBI) [9] to interconnect soft core CPUs and Intellectual Property (IP) blocks on FPGA. This paper extends the study presented in [10].…”

Scalable Architecture for SoC Video Encoders

“…The simplest version of HIBI has a FIFO-based wrapper for connecting IP-blocks [18]. The HIBI interface supports also more complex interfaces such as the VCI [21] or OCP [22].…”

“…In our approach, the encoder architecture is based on scalable homogeneous multiprocessing and a SoC communication network called HIBI [18]. The encoder architecture follows Single Program Multiple Data (SPMD) model of parallelism and the master-slave processor configuration.…”

“…It facilitates the separation of communication from computation both on application and architecture levels. In the architecture, the communication between IP-blocks is realized with the HIBI network [18]. HIBI is well-suited for streaming transfers that is inherent in video encoding because of its high throughput and low latency.…”