Highly reliable BEOL-transistor with oxygen-controlled InGaZnO and Gate/Drain offset design for high/low voltage bridging I/O operations

Kaneko, K.; Inoue, N.; Saito, Shinobu; Furutake, N.; Sunamura, H.; Kawahara, J.; Hane, M.; Hayashi, Y.

doi:10.1109/iedm.2011.6131507

Cited by 43 publications

(19 citation statements)

References 3 publications

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“…Furthermore, by taking advantage of the wide bandgap of a-IGZO, a-IGZO TFTs have been investigated as high-voltage power transistors, which can be integrated monolithically with logic circuits for reducing the overhead of additional power management circuits at the I/O interface. [8][9][10] For power transistor applications, bias stress instability in a high field and at an elevated temperature is the foremost concern. 9 The a-IGZO TFTs are prone to a positive threshold voltage shift (DV T ) induced by electron trapping in gate dielectrics during positive bias stress (PBS) [11][12][13] and are prone to a negative DV T induced by hole trapping during negative bias stress (NBS), especially when assisted by photons and subgap defects under illumination.…”

mentioning

confidence: 99%

Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al2O3 gate dielectric

Chang

Ming

Lin

et al. 2016

Applied Physics Letters

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Low-temperature atomic layer deposition (ALD) was employed to deposit Al 2 O 3 as a gate dielectric in amorphous In-Ga-Zn-O thin-film transistors fabricated at temperatures below 120 C. The devices exhibited a negligible threshold voltage shift (DV T) during negative bias stress, but a more pronounced DV T under positive bias stress with a characteristic turnaround behavior from a positive DV T to a negative DV T. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive DV T , which can be fitted using the stretched exponential function. The breakage of residual AlO-H bonds in low-temperature ALD Al 2 O 3 is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In-Ga-Zn-O channel and induce the negative DV T through electron doping with power-law time dependence. A rapid partial recovery of the negative DV T after stress is also observed during relaxation. V

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mentioning

confidence: 99%

Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al2O3 gate dielectric

Chang

Ming

Lin

et al. 2016

Applied Physics Letters

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“…HIN-film transistors (TFTs) based on amorphous oxide semiconductors (AOSs), like amorphous InGaZnO (a-IGZO), have been demonstrated to possess ultra-low offcurrent (I off ), steep subthreshold swing (SS), relatively high mobility, and low fabrication temperature, and thus are regarded as the most viable driving device for next-generation displays [1]. The overall competitiveness of AOSs further attracts extensive attention in large-area flexible electronics [2], low-power circuits [3], flexible chips [4], 3D stacked memories [5], and other back-end-of-line (BEOL) devices for 3D ICs [6]. These applications demand the AOS transistors with extremely downscaled channel length (L) and accordingly gate insulator (GI) thickness [7], [8].…”

Section: Introductionmentioning

confidence: 99%

High-Performance Self-Aligned Top-Gate Amorphous InGaZnO TFTs With 4 nm-Thick Atomic-Layer-Deposited AlO_x Insulator

Zhang

Wang

et al. 2022

IEEE Electron Device Lett.

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Electrical characteristics of self-aligned topgate (SATG) amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with 4 nm-thick atomic-layer-deposited (ALD) AlOx gate insulator (GI) are investigated. It is demonstrated that the SATG a-IGZO TFTs present highperformance metrics including a near-ideal subthreshold swing (SS) of 60.9 mV/dec, a low off-state current below 10 −12 A, a positive Vth of 0.1 V, and a decent mobility of 14.1 cm 2 /V•s. In addition, the TFTs exhibit negligible Vth shifts less than 0.02 V against electrical bias stresses. Both high performance and excellent stability are thus simultaneously achieved for the ultrathin GI of amorphous oxide semiconductor (AOS) TFTs.

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“…Additionally, thanks to its large bandgap energy (~ 3eV), OSchannel FET shows unique features such as high breakdown voltage (VBD >40 V) and extremely low off-state leakage current (<10 -22 A/m). These attractive features can open a new application of OS-FET as BEOL transistors for 3D integrated CMOS-LSI such as high voltage I/Os and embedded memory [2,3,4]. In order to shrink its feature size from micrometer to nanometer range for CMOS-LSI application, a vertical-channel FET is the most promising device architecture.…”

Section: Introductionmentioning

confidence: 99%

7‐2: Invited Paper: A 40 nm Gate Length Surrounding Gate Vertical‐Channel FET Using Thermally Stable In‐Al‐Zn‐O Channel for 3D CMOS‐LSI Applications

Sato¹,

Fujiwara²,

Saito³

et al. 2021

Symp Digest of Tech Papers

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We have developed a CMOS back‐end‐of‐line (BEOL) process compatible oxide semiconductor channel FET with newly proposed In‐Al‐Zn‐O (IAZO) for 3D CMOS‐LSI applications. Compared with In‐Ga‐Zn‐O for active‐matrix display applications, IAZO channel has higher thermal stability (~420°C) suitable for BEOL transistors where suppression of channel shortening is essential. We have successfully demonstrated a surrounding gate vertical‐channel FET with gate length of 40 nm by IAZO channel.

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Highly reliable BEOL-transistor with oxygen-controlled InGaZnO and Gate/Drain offset design for high/low voltage bridging I/O operations

Cited by 43 publications

References 3 publications

Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al2O3 gate dielectric

Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al2O3 gate dielectric

High-Performance Self-Aligned Top-Gate Amorphous InGaZnO TFTs With 4 nm-Thick Atomic-Layer-Deposited AlO_x Insulator

7‐2: Invited Paper: A 40 nm Gate Length Surrounding Gate Vertical‐Channel FET Using Thermally Stable In‐Al‐Zn‐O Channel for 3D CMOS‐LSI Applications

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Highly reliable BEOL-transistor with oxygen-controlled InGaZnO and Gate/Drain offset design for high/low voltage bridging I/O operations

Cited by 43 publications

References 3 publications

Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al2O3 gate dielectric

Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al2O3 gate dielectric

High-Performance Self-Aligned Top-Gate Amorphous InGaZnO TFTs With 4 nm-Thick Atomic-Layer-Deposited AlOx Insulator

7‐2: Invited Paper: A 40 nm Gate Length Surrounding Gate Vertical‐Channel FET Using Thermally Stable In‐Al‐Zn‐O Channel for 3D CMOS‐LSI Applications

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High-Performance Self-Aligned Top-Gate Amorphous InGaZnO TFTs With 4 nm-Thick Atomic-Layer-Deposited AlO_x Insulator