Highly Reliable and Manufacturable Ultrafine Pitch Cu–Cu Interconnections for Chip-Last Embedding With Chip-First Benefits

Abstract

Flip-chip packaging of Ultrafine pitch integrated circuits aggravates the stress-strain concerns as the interconnection pitch is decreased, requiring a fundamentally different system approach to interconnections, underfill processes and interfaces, and the substrate. This paper demonstrates an innovative and manufacturable solution to achieve excellent reliability at Ultrafine pitch (∼30 µm) using direct copper-copper (Cu-Cu) interconnections with adhesives. A number of 30-µm bump pitch test vehicles (TVs) were designed with 3 mm × 3 mm chips to extract both daisy chain resistance and singlebump resistance data. Assembled bump resistivity was found to be ∼3-4× lower than most solders. Performance of these TVs was studied for high temperature storage (HTS) life test, unbiased-highly accelerated stress test (U-HAST) and thermal cycling test (TCT). Test results showed that the assemblies with this next generation interconnection technology depicted excellent reliability results in HTS, U-HAST, and TCT tests. Based on these results, it is concluded that adhesive materials, provide unique opportunities for Ultrafine pitch and high performance interconnections.

Modeling, design, and demonstration of low-temperature Cu interconnections to ultra-thin glass interposers at 20 μm pitch

“…In conjunction with the polymer adhesive that bonds the chip and the substrate, this results in high thermomechanical and electromigration reliability as previously shown by Kumbhat et al [4]. The bonding conditions such as load, temperature and cycle time determine the extent of metallurgical bonding and overall reliability.…”

Ultra-thin and ultra-high I/O density package-on-package (3D Thin PoP) for high bandwidth of smart systems

“…The newly -developed and patented low temperature Cu-Cu thermo-compression bonding process was used to assemble 50µm thin Si test chips of 7mm x7mm size [8]. Figure 5 (d) shows the bumped wafer for Cu-Cu interconnections.…”

“…Vertical vias at fine pitch of 80µm are pre-fabricated in the cavity layers. Ultra-thin and large ICs are then assembled inside the cavities using a new patented low temperature Cu-Cu bonding process developed by Georgia Tech [8]. This results in a single package thickness of 150µm including die thickness of 50-75µm.…”

3D IPAC — A new passives and actives concept for ultra-miniaturized electronic and bioelectronic functional modules

“…3D IPAC modules will use customized designs for power, RF and digital applications based on the applications, power requirements and performance-cost trade-offs. Major breakthrough technologies in 3D IPAC [10] and fine-pitch interconnections [11,12] have recently been demonstrated by GT-PRC. The key passive component technologies in 3D IPAC are high-density capacitors, high-density inductors, and high Q RF components, which form the primary focus of this paper.…”