A textured calcium phosphate based bio-ceramic coating was synthesized by continuous wave Nd:YAG laser induced direct melting of hydroxyapatite precursor on Ti-6Al-4V substrate. Two different micro-textured patterns (100 μm and 200 μm line spacing) of Ca-P based phases were fabricated by this technique to understand the alignment and focal adhesion of the bone forming cells on these surfaces. X-ray diffraction studies of the coated samples indicated the presence of CaTiO₃, α-Ca₃(PO₄)₂, Ca(OH)₂, TiO₂ (anatase) and TiO₂ (rutile) phases as a result of the intermixing between the precursor and substrate material during laser processing. A two dimensional elemental mapping of the cross-section of the coated samples exhibited the presence of higher phosphorous concentration within the coating and a thin layer of calcium concentration only at the top of the coating. Improved in vitro bioactivity and in vitro biocompatibility was observed for the laser processed samples as compared to the control.
This work introduces a simple process to fabricate 3D metallic structures with micro to nano-sized features. Star-shaped gold catalysts were fabricated using electron beam lithography and used as catalysts in MaCE to form spiraling 3D structures. High fidelity was verified by adding 30 nm wide holes in some catalysts for form 30 nm wide spiraling silicon pillars. The gold catalyst remaining at the bottom of the 3D MaCE template was used as a seed for electroless deposition of Pd and the resulting structure extracted using tetramethylammonium hydroxide to form a freestanding 3D metallic structure with nano-sized 3D spiraling holes.Many useful devices are created by the act of forming a small hole and filling it with metal. For example, thru-silicon-vias used in 3D electronic packaging are fabricated by etching a hole in silicon and filling it with copper to serve as an electrical interconnect, 1,2 while optical waveguides often consist of small channels filled with silver or gold. [3][4][5] Large volume manufacturing has shown that planar 2D nanostructures, such as microelectromechanical systems (MEMS) and transistors, can be fabricated using a mix of photolithography, etching, and electroless filling techniques; however, 3D templates are typically difficult to fabricate and fill on this small scale. The problem can readily be attributed to the fact that, like many processes, both fabricating and filling templates becomes increasingly difficult as feature sizes approach the sub-micron to nano-sized domains. As a result, trade-offs between structure complexity and manufacturability are often made.The root cause of this limitation can be traced to the constraints of current nanofabrication frameworks that are heavily dependent on wet chemical and dry etching processes centered around stationary masks used in combination with lithography and thin-film deposition/growth processes. While this combination is widely used to form cantilevers, MEMS, photonic devices, and more, 6 these shapes are generally limited to simple undercuts or buildups of 2D patterns and require multiple lithography, etching, and deposition cycles to create a 2.5D structure consisting predominately of planar, 2D objects stacked horizontally on top of each other. 7 Overall, this process can be extremely time consuming, has limited feature fidelity, and is expensive. 8,9 The problem of 3D fabrication is further exacerbated by the difficulties of filling templates that have complex 3D geometry and/or high aspect ratios, as evaporation and sputter processes are not well suited for filling these structures. 10 Luckily, electrochemical and electroless deposition techniques can be used to fill sub-micron templates with high feature fidelity in cases where either a metal ground plane or seed layer is available at the bottom of the template. As long as these features are present, the structures fabricated using electrochemical and electroless deposition are typically limited to the capabilities of the process used to define the template itself. As such, a ...
Package-on-package (PoP) technologies used in smart phones and tablets are reaching limits in logic-to-memory bandwidth and in thickness reduction. Advances in PoP including through-mold vias (TMVs) and low-CTE, highmodulus laminate substrates have not been able to overcome the I/O density and thickness limitations to date. To overcome these barriers, two major technologies have been pursued. The first approach is chip-first embedding in organic dielectrics and in fan-out wafer level packages. While this can achieve higher I/O's, they face many challenges that include large-die reliability, intermediate testability for higher yield, thermal dissipation, and new supply-chain model. The second approach to address the need is the so-called wide-I/O logic and memory stacking with through silicon vias (TSVs), which promises highest bandwidth in lowest profile, but is viewed as too complex and costly due to TSV integration in logic IC. Georgia Tech PRC proposes and demonstrates, for the first time, a third approach that is more manufacturable and costeffective. This is referred to as 3D Thin PoP -a more advanced 3-dimensional POP, -designed to achieve ultra-thin stacked packages in 3D with higher chip-to package and package-to-package I/Os to achieve higher bandwidth. This paper reports a number of breakthrough advances in 3D Thin PoP, thus providing a path to extend PoP. These innovations fall into three areas that include: (a) Ultra-thin, 150µm thick organic substrate with multiple layers of build-up wiring with precision cavities ready for chip assembly, (b) die-to-package Cu-Cu interconnections at 30µm pitch bonded at 160 o C, and (c) package-on-package stacking with 50µm interconnect pitch. Low signal losses are achieved by having shorter chipto-chip I/O's and lower stand-off interconnections. These innovations enable higher bandwidth in 3D Thin PoP by virtue of 8x improvement in I/Os combined with 2-3x reduction in total thickness over current PoP.
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