Highly Manufacturable Double-Gate FinFET With Gate-Source/Drain Underlap

Yang, Ji-Woon; Zeitzoff, P.; Tseng, Hsing‐Huang

doi:10.1109/ted.2007.896387

Cited by 58 publications

(28 citation statements)

References 15 publications

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“…Transistors used in the conventional SRAM cell are symmetrically gate-to-source and gate-to-drain underlapped six FinFETs [17,22,23,[31][32][33]. The symmetrically gate-underlapped FinFETs (FinFET-Sym) are designed and optimized to match the International Technology Roadmap for Semiconductors (ITRS) [5] projections for 15 nm FinFET technology node.…”

Section: Conventional Symmetrical Six-finfet Sram Cellmentioning

confidence: 99%

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

Salahuddin

Kursun

Jiao³

2015

Transactions on Electrical and Electronic Materials

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Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology. Keywords

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Section: Conventional Symmetrical Six-finfet Sram Cellmentioning

confidence: 99%

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

Salahuddin

Kursun

Jiao³

2015

Transactions on Electrical and Electronic Materials

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“…SDE region engineering is considered by the application of overlap and underlap design. Abrupt junction, which is achievable by solid re-growth and laser annealing process [5], is designed with a fast doping decay with lateral straggle (σ S/D ) at the value of 1 nm/dev at the edge of SDE region whereas the underlap doping profile in the SDE region is simulated with a Gaussian model rolling off from a peak value of 10 20 cm -3 at the edge of the source/drain. The equivalent oxide thickness (EOT) of the Hf-based dielectric in the simulation is 0.7 nm.…”

Section: Base Finfet Unitmentioning

confidence: 99%

“…Several papers present work on source/ drain extension (SDE) region engineering with the goal of improving a single-fin FET or coupling FinFETs performance (N FinFET ≤ 5) [3][4][5]. Only few papers are on analog/RF FoM of multi-fin FETs which introduces a large total channel width to achieve high transconductance, maintain good noise and mismatch performance [2].…”

Section: Introductionmentioning

confidence: 99%

Design Consideration in the Development of Multi-Fin FETs for RF Applications

Feng¹,

Ghosh²

2012

WJNSE

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In this paper, we propose multi-fin FET design techniques targeted for RF applications. Overlap and underlap design configuration in a base FinFET are compared first and then multi-fin device (consisting of transistor unit up to 50) is studied to develop design limitations and to evaluate their effects on the device performance. We have also investigated the impact of the number of fins (up to 50) in multi-fin structure and resulting RF parameters. Our results show that as the number of fin increases, underlap design compromises RF performance and short channel effects. The results provide technical understanding that is necessary to realize new opportunities for RF and analog mixed-signal design with nanoscale FinFETs.

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“…Optimized doping profile in the SDE regions is given with the tradeoff between parasitic capacitances and resistance [39]. It is found that the best case for SNWTs is gate overlap architecture, which is different from the favorable gate underlap structure of double-gate MOSFETs [40,41]. This is because of the stringent requirement of parasitic resistance reduction but less sensitivity of the parasitic capacitance to the SDE doping gradient compared with double-gate MOSFETs, due to the dominant outer-fringing capacitance, and excellent gate controllability of the GAA structure.…”

Section: B Parasitic Effects In Snwtsmentioning

confidence: 99%

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

Huang

Wang

Zhuge

et al. 2011

2011 IEEE Custom Integrated Circuits Conference (CICC)

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The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the characterization and analysis of this unique one-dimensional nanowire-channel device with three-dimensional surrounding-gate from experiments and simulation, including carrier transport behavior, parasitic effects, noise characteristics, self-heating effect, variability and reliability, which can provide useful information for the GAA device hierarchical modeling and device/circuit co-design.

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Highly Manufacturable Double-Gate FinFET With Gate-Source/Drain Underlap

Cited by 58 publications

References 15 publications

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

Design Consideration in the Development of Multi-Fin FETs for RF Applications

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

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