2012
DOI: 10.4236/wjnse.2012.22011
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Design Consideration in the Development of Multi-Fin FETs for RF Applications

Abstract: In this paper, we propose multi-fin FET design techniques targeted for RF applications. Overlap and underlap design configuration in a base FinFET are compared first and then multi-fin device (consisting of transistor unit up to 50) is studied to develop design limitations and to evaluate their effects on the device performance. We have also investigated the impact of the number of fins (up to 50) in multi-fin structure and resulting RF parameters. Our results show that as the number of fin increases, underlap… Show more

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Cited by 15 publications
(2 citation statements)
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“…Reference [21] proposed a model for parasitic gate capacitances and gate resistance in multi‐fin double gate (DG) FinFET architecture and found that the device provides the lowest value of equivalent resistance with lesser device delay. In Reference [22], it is reported that multi‐Fin FET structure is very useful for radio frequency (RF) application where underlap multi‐Fin FET improves SCSs effect and the cost of multi‐Fin FET device is lower than hetero‐junction devices. Sankatali el al 23 .…”
Section: Introductionmentioning
confidence: 99%
“…Reference [21] proposed a model for parasitic gate capacitances and gate resistance in multi‐fin double gate (DG) FinFET architecture and found that the device provides the lowest value of equivalent resistance with lesser device delay. In Reference [22], it is reported that multi‐Fin FET structure is very useful for radio frequency (RF) application where underlap multi‐Fin FET improves SCSs effect and the cost of multi‐Fin FET device is lower than hetero‐junction devices. Sankatali el al 23 .…”
Section: Introductionmentioning
confidence: 99%
“…To utilize this feature, designs with minimal channelseparation (i.e., the distance of pitch) are needed to accommodate more channels so that high-packing density can be achieved. However, there are merely few works that specifically examined the effect of fin width, increased channel number, and resistive and capacitive analyses for TFETs [10]- [12]. Thus, a study that correlates to multi-channel along with minimal channel separation or inter-gate separation (IGS) is further needed.…”
Section: Introductionmentioning
confidence: 99%