High-Speed Through Silicon Via(TSV) Filling Using Diallylamine Additive

Hayashi, Tarō; Kondo, Kazuo; Saito, Takeyasu; Takeuchi, Mitsuhiro; Okamoto, Naoki

doi:10.1149/2.076112jes

Cited by 69 publications

(59 citation statements)

References 7 publications

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“…6,9,13 The Fig. 3a, conical surfaces resulted from the columnar TSVs filling which used the PPR current, and the standard four-additive electrolyte including Cl − , SPS, PEG, and SDDACC.…”

Section: Resultsmentioning

confidence: 99%

Communication—Conical TSV Filling within 30 Seconds

Hoang

Kondo

2017

J. Electrochem. Soc.

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Super bottom up filling of TSVs is achieved by using a new leveler NM. The leveler was characterized by CVS method, its inhibition role was exhibited at different rotating rates and concentrations. NM electrolyte built up TSVs from the bottoms and almost no deposition on the TSV walls. The electrolyte containing NM leveler was effective at a high current density for both periodic pulse reverse (PPR) current, and direct current (DC). The 2 μm diameter and 16 μm depth conical TSVs required 30 s for full filling by two steps which were the PPR current step and the DC step.

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Section: Resultsmentioning

confidence: 99%

Communication—Conical TSV Filling within 30 Seconds

Hoang

Kondo

2017

J. Electrochem. Soc.

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“…By using electrodeposition of copper, very shallow TSVs with a depth of just 70 μm can typically be filled in about 35 min [8], while deeper TSVs of 390 μm depth may take as much as 12 h to fill [9]. Substrates with shallow TSVs have to be thinned after the filling, which drastically increases fabrication costs and further reduces the throughput.…”

Section: Discussionmentioning

confidence: 99%

“…Electrodeposition and CVD processes are well established in the semiconductor industry and are widely available. However, these kinds of processes typically suffer from long processing times and are limited in the achievable aspect ratios of the TSVs [8,9]. Especially electrodeposition of copper has proven to be challenging for implementing void-free filling of highaspect ratio TSVs [5,10,11].…”

Section: Introductionmentioning

confidence: 99%

High-speed metal-filling of through-silicon vias (TSVs) by parallelized magnetic assembly of micro-wires

Bleiker

Fischer

Niklaus

2016

2016 IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS)

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This work reports a parallelized magnetic assembly method for scalable and cost-effective through-silicon via (TSV) fabrication. Our fabrication approach achieves high throughput by utilizing multiple magnets below the substrate to assemble TSV structures on many dies in parallel. Experimental results show simultaneous filling of four arrays of TSVs on a single substrate, with 100 via-holes each, in less than 20 seconds. We demonstrate that increasing the degree of parallelization by employing more assembly magnets below the substrate has no negative effect on the TSV filling speed or yield, thus enabling scaled-up TSV fabrication on full wafer-level. This method shows potential for industrial application with an estimated throughput of more than 70 wafers per hour in one single fabrication module. Such a TSV fabrication process could offer shorter processing times as well as higher obtainable aspect ratios compared to conventional TSV filling methods.

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“…[6][7][8][9][10][11][12][13] Copper is a good conductor but its coefficient of thermal expansion (CTE) is high. Therefore, issues related to CTE mismatch between the conducting materials and the dielectric materials arise in PCB and 3D packaging with high-density interconnections.…”

mentioning

confidence: 99%

“…[1][2][3][4][5] Recently, through-silicon vias (TSVs) have also been metallized by copper electroplating for the interconnection of threedimensional (3D) IC chip stacking packaging. [6][7][8][9][10][11][12][13] Copper is a good conductor but its coefficient of thermal expansion (CTE) is high. Therefore, issues related to CTE mismatch between the conducting materials and the dielectric materials arise in PCB and 3D packaging with high-density interconnections.…”

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confidence: 99%

Microvia Filling with Nickel-Tungsten Alloy to Decrease the Coefficient of Thermal Expansion of Electronic Circuit Interconnections

Lin

Huang

Wang

et al. 2015

ECS Electrochemistry Letters

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A nickel-tungsten alloy plating formula was developed to electrochemically fill the microvias of printed circuit boards and the through-silicon vias (TSVs) of wafers. The plating solution was composed of Ni(SO 3 NH 2 ) 2 , citric acid, sodium citrate, Na 2 WO 4 , chloride ions, and 2-mercapto-5-benzimidazolesulfonic acid. A void-free Ni-W superfilling of a microvia and a TSV were achieved. The tungsten content in the filled alloy varied from 1.5 atom% to 5.5 atom%, depending on the plating temperature. The coefficient of thermal expansion of the filled Ni-W was theoretically calculated according the tungsten content, which was lower than that of copper. Microvia filling by copper electroplating has been widely employed to fabricate state-of-the-art printed circuit boards (PCBs) for interconnection, especially for integrated circuit (IC) packaging substrates.1-5 Recently, through-silicon vias (TSVs) have also been metallized by copper electroplating for the interconnection of threedimensional (3D) IC chip stacking packaging. [6][7][8][9][10][11][12][13] Copper is a good conductor but its coefficient of thermal expansion (CTE) is high. Therefore, issues related to CTE mismatch between the conducting materials and the dielectric materials arise in PCB and 3D packaging with high-density interconnections.Numerous authors have reported that the high CTE of the copper filled in the TSVs results in stress impacts on silicon substrates. [14][15][16][17] Copper atoms diffuse from the TSV due to thermal cycling, leading to void formation in the TSV. 18,19 The copper protrusion on the TSV caused respectively by thermal expansion and diffusion of copper lattices and atoms may destroy stacked IC chips. [20][21][22] Copper must be replaced by tungsten 23 or nickel 24,25 to overcome the issue of CTE mismatch.Although the CTE of tungsten is very low, 14,26 it cannot be electrochemically plated in an aqueous electrolyte. Fortunately, tungsten can be induced to co-deposit with nickel. [27][28][29][30][31][32] In this work, a Ni-W alloy plating formula that can achieve Ni-W bottom-up filling of microvia was developed. This plating formula can fill the microvia of PCBs and can also fill TSVs. The Ni-W filled TSVs exhibit good thermal stability after being annealed at 500• C for 4 h. ExperimentalThe dimensions of the PCB fragments cut for the Ni-W filling plating were 4.2 × 6.0 cm 2 . The microvias were formed by CO 2 laser ablation. The diameter and depth of the microvias were 80 μm and 40 μm, respectively. The sidewalls of the microvias were metallized by electroless copper plating in advance to deposit a 2-3 μm thick layer of copper before the filling plating.TSVs were formed by a deep reactive ion etching (DRIE) process (i.e., the Bosch process). The thickness of the isolation layer (i.e., SiO 2 ) in the TSVs formed by thermal oxidation was approximately 1-3 × 10 3 Å. The barrier layer was a TiN film with a thickness of 500 Å, which was conformably deposited by atomic layer deposition (ALD) for 600 cycles. The seed layer was depo...

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High-Speed Through Silicon Via(TSV) Filling Using Diallylamine Additive

Cited by 69 publications

References 7 publications

Communication—Conical TSV Filling within 30 Seconds

Communication—Conical TSV Filling within 30 Seconds

High-speed metal-filling of through-silicon vias (TSVs) by parallelized magnetic assembly of micro-wires

Microvia Filling with Nickel-Tungsten Alloy to Decrease the Coefficient of Thermal Expansion of Electronic Circuit Interconnections

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