High-Speed and Low-Power PID Structures for Embedded Applications

Oudjida, Abdelkrim K.; Chaillet, Nicolas; Liacha, Ahmed; Hamerlain, Mustapha; Berrandjia, Mohamed L.

doi:10.1007/978-3-642-24154-3_26

Cited by 5 publications

(6 citation statements)

References 14 publications

(14 reference statements)

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“…For r ranging from 8 to 64, ß''2 8 is the fastest algorithm, but it is outperformed by ß2 32 for r values greater than 64. ß2 2 algorithm served to design a 16-bit set-point PID. The implementation results outperformed the published ones at all levels [7]. …”

Section: Multiplication Algorithmcontrasting

confidence: 54%

New high-speed and low-power radix-2r multiplication algorithms

Oudjida

Liacha

Berrandjia

et al. 2012

2012 IEEE Faible Tension Faible Consommation

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In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (N/r), but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix (r≥3) multiplication. Based on a mathematical proof that any higher radix-2 r can be recursively derived from a combination of two or a number of lower radices, a series of generalized radix-2 r multipliers are generated by means of primary radices: 2 1 , 2 2 , 2 5 , and 2 8 . A variety of higher-radix (2 3 -2 32 ) two's complement 64x64 bit serial/parallel multipliers are implemented on Virtex-6 FPGA and characterized in terms of multiply-time, energy consumption per multiply-operation, and area occupation for r value varying from 2 to 64. Compared to a recent published algorithm, savings of 21%, 53%, 105% are respectively obtained in terms of speed, power, and area.

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Section: Multiplication Algorithmcontrasting

confidence: 54%

New high-speed and low-power radix-2r multiplication algorithms

Oudjida

Liacha

Berrandjia

et al. 2012

2012 IEEE Faible Tension Faible Consommation

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show abstract

“…ß2 2 algorithm served to design a scalable 16-bit setpoint PID controller employing five multiplication cores. The implementation results outperformed the published ones at all levels [14].…”

Section: Based On Theory and Implementation Results It Is Set Clear mentioning

confidence: 79%

“…3), targeting applications where the serialization of multiplication is mandatory. This is the case for instance in embedded digital PID (Peripheral Integral Derivative) controller where five multiplication cores are required [14], or for high-precision or very large operand size applications (cryptography) where a fully-parallel n×n bit implementation is excluded.…”

Section: B Radix 2 4 Recodingmentioning

confidence: 99%

A New Recursive Multibit Recoding Algorithm for High-Speed and Low-Power Multiplier

Oudjida¹,

Chaillet²,

Liacha³

et al. 2012

Journal of Low Power Electronics

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“…A double-recursive (s=2) version of equation (15) served to design a scalable 16-bit setpoint Finite-Word-Length PID controller, employing five multiplication cores. The implementation results outperformed the published ones at all levels [23].…”

Section: B Delaymentioning

confidence: 79%