A New High Radix-2&lt;SUP&gt;r&lt;/SUP&gt; (&lt;I&gt;r&lt;/I&gt; ≥ 8) Multibit Recoding Algorithm for Large Operand Size (&lt;I&gt;N&lt;/I&gt; ≥ 32) Multipliers

Oudjida, Abdelkrim K.; Chaillet, Nicolas; Berrandjia, Mohamed L.; Liacha, Ahmed

doi:10.1166/jolpe.2013.1240

Cited by 8 publications

(2 citation statements)

References 16 publications

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“…It has been demonstrated that the hardware cost of a binary adder rises linearly with the operand size. In contrast, the implementation cost of a hardwired multiplier escalates quadratically with the operand size [46]. Hence, reducing the number of multipliers, even if it results in a slight increase in the number of adders, significantly influences the hardware implementation of digital filtering cores.…”

Section: Implementation Complexitymentioning

confidence: 99%

VLSI-Friendly Filtering Algorithms for Deep Neural Networks

2023

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The paper introduces a range of efficient algorithmic solutions for implementing the fundamental filtering operation in convolutional layers of convolutional neural networks on fully parallel hardware. Specifically, these operations involve computing M inner products between neighbouring vectors generated by a sliding time window from the input data stream and an M-tap finite impulse response filter. By leveraging the factorisation of the Hankel matrix, we have successfully reduced the multiplicative complexity of the matrix-vector product calculation. This approach has been applied to develop fully parallel and resource-efficient algorithms for M values of 3, 5, 7, and 9. The fully parallel hardware implementation of our proposed algorithms achieves approximately a 30% reduction in embedded multipliers compared to the naive calculation methods.

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Section: Implementation Complexitymentioning

confidence: 99%

VLSI-Friendly Filtering Algorithms for Deep Neural Networks

2023

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“…Reducing the number of multipliers is especially important in the design of specialized fully parallel ASIC-based processors because minimizing the number of necessary multipliers reduces power dissipation and lowers the cost implementation of the entire system being implemented. It is proved that the implementation complexity of a hardwired multiplier grows quadratically with operand size, while the hardware complexity of a binary adder increases linearly with operand size [28]. Therefore, a reduction in the number of multipliers, even at the cost of a small increase in the number of adders, has a significant role in the ASIC-based implementation of the algorithm.…”

Section: Implementation Complexitymentioning

confidence: 99%

Some Algorithms for Computing Short-Length Linear Convolution

Cariow

Papliński

2020

Electronics

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In this article, we propose a set of efficient algorithmic solutions for computing short linear convolutions focused on hardware implementation in VLSI. We consider convolutions for sequences of length N= 2, 3, 4, 5, 6, 7, and 8. Hardwired units that implement these algorithms can be used as building blocks when designing VLSI -based accelerators for more complex data processing systems. The proposed algorithms are focused on fully parallel hardware implementation, but compared to the naive approach to fully parallel hardware implementation, they require from 25% to about 60% less, depending on the length N and hardware multipliers. Since the multiplier takes up a much larger area on the chip than the adder and consumes more power, the proposed algorithms are resource-efficient and energy-efficient in terms of their hardware implementation.

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Minimal Filtering Algorithms for Convolutional Neural Networks

Cariow

Cariowa

2021

Studies in Computational Intelligence

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A New High Radix-2<SUP>r</SUP> (<I>r</I> ≥ 8) Multibit Recoding Algorithm for Large Operand Size (<I>N</I> ≥ 32) Multipliers

Cited by 8 publications

References 16 publications

VLSI-Friendly Filtering Algorithms for Deep Neural Networks

VLSI-Friendly Filtering Algorithms for Deep Neural Networks

Some Algorithms for Computing Short-Length Linear Convolution

Minimal Filtering Algorithms for Convolutional Neural Networks

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