Some Algorithms for Computing Short-Length Linear Convolution

We propose an asynchronous acoustic chirp slope keying to map short bit sequences on single or multiple bands without preamble or error correction coding on the physical layer. We introduce a symbol detection scheme in the demodulator that uses the superposed matched filter results of up and down chirp references to estimate the symbol timing, which removes the requirement of a preamble for symbol synchronization. Details of the implementation are disclosed and discussed, and the performance is verified in a pool measurement on laboratory scale, as well as the simulation for a channel containing Rayleigh fading and Additive White Gaussian Noise. For time-bandwidth products (TB) of 50 in single band mode, a raw data rate of 100 bit/s is simulated to achieve bit error rates (BER) below 0.001 for signal-to-noise ratios above −6 dB. In dual-band mode, for TB of 25 and a data rate of 200 bit/s, the same bit error level was achieved for signal-to-noise ratios above 0 dB. The simulated packet error rates (PER) follow the general behavior of the BER, but with a higher error probability, which increases with the length of bits in each packet.

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“…The output sequence is transferred into an analog signal

, e.g., by a DAC, amplified by the PA and transmitted. Alternatively, this modulation can be calculated by zero-padding the multiplexed bit sequences

by length

and convolving the resulting sequence with the reference signal

, but this approach is neither efficient in memory usage, nor the calculation steps required [ 49 ].…”

Section: Methodsmentioning

confidence: 99%

Asynchronous Chirp Slope Keying for Underwater Acoustic Communication

Schott

Gabbrielli

Xiong

et al. 2021

Sensors

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“…2) Convolution operation: Fixed iteration count loops are a key mechanism for implementing the convolution operation [21] in convolutional neural networks (CNNs) [22]- [23]. It involves looping over the elements of the input feature map and the convolution kernel, performing multiplication and accumulation operations to generate the output feature map.…”

Section: Application Of Fixed Iteration Count Loopsmentioning

confidence: 99%

Research on Compilation Methods for Fixed Iteration Count Loop Dual-Mode Unrolling in VLIW Architectures

2024

JSSH

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Loop unrolling is a commonly used optimization technique in VLIW architectures that increases the number of executable instructions in code, thereby improving instruction-level parallelism. However, existing loop unrolling techniques often include a significant number of loop condition instructions and induction variable update instructions, which consume various register resources and result in additional power consumption. In this paper, we propose a loop compilation optimization method based on basic loop unrolling techniques, focusing on fixed iteration count loops and employing dual-mode unrolling. This method eliminates the loop structure, enhances instruction-level parallelism, and improves the flexibility of subsequent instruction scheduling. We describe the compilation optimization process of this dual-mode unrolling approach. Finally, we conduct experimental research using the FT-M7002 hardware platform. The experimental results demonstrate that our dual-mode unrolling method achieves an average performance improvement of 5% to 8% compared to basic loop unrolling techniques.

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“…Ma et al [17] described a performance model to evaluate the performance and resource utilization of CNN inference implemented in FPGA. The authors of [18,19] proposed hardware-oriented algorithms for computing convolutions.…”

Section: Related Workmentioning

confidence: 99%

An FPGA-Based LSTM Acceleration Engine for Deep Learning Frameworks

et al. 2021

Electronics

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Over the past two decades, Long Short-Term Memory (LSTM) networks have been used to solve problems that require modeling of long sequence because they can selectively remember certain patterns over a long period, thus outperforming traditional feed-forward neural networks and Recurrent Neural Network (RNN) on learning long-term dependencies. However, LSTM is characterized by feedback dependence, which limits the high parallelism of general-purpose processors such as CPU and GPU. Besides, in terms of the energy efficiency of data center applications, the high consumption of GPU and CPU computing cannot be ignored. To deal with the above problems, Field Programmable Gate Array (FPGA) is becoming an ideal alternative. FPGA has the characteristics of low power consumption and low latency, which are helpful for the acceleration and optimization of LSTM and other RNNs. This paper proposes an implementation scheme of the LSTM network acceleration engine based on FPGA and further optimizes the implementation through fixed-point arithmetic, systolic array and lookup table for nonlinear function. On this basis, for easy deployment and application, we integrate the proposed acceleration engine into Caffe, one of the most popular deep learning frameworks. Experimental results show that, compared with CPU and GPU, the FPGA-based acceleration engine can achieve performance improvement of 8.8 and 2.2 times and energy efficiency improvement of 16.9 and 9.6 times, respectively, within Caffe framework.

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Some Algorithms for Computing Short-Length Linear Convolution

Cited by 4 publications

References 27 publications

Asynchronous Chirp Slope Keying for Underwater Acoustic Communication

Asynchronous Chirp Slope Keying for Underwater Acoustic Communication

Research on Compilation Methods for Fixed Iteration Count Loop Dual-Mode Unrolling in VLIW Architectures

An FPGA-Based LSTM Acceleration Engine for Deep Learning Frameworks

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