A New Recursive Multibit Recoding Algorithm for High-Speed and Low-Power Multiplier

Oudjida, Abdelkrim K.; Chaillet, Nicolas; Liacha, Ahmed; Berrandjia, Mohamed L.

doi:10.1166/jolpe.2012.1217

Cited by 10 publications

(8 citation statements)

References 13 publications

(47 reference statements)

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“…• A series of new multi-precision multiplication algorithms, offering the possibility to run simultaneously several small-size multiplications on the same N×N-bit multiplication array [7]. The proposed algorithms have the superiority over exiting ones to support a generic partitioning of the array.…”

Section: Our Contribution In the Binary Arithmeticmentioning

confidence: 99%

A new binary arithmetic for finite-word-length linear controllers: MEMS applications

Oudjida

Liacha

Berrandjia

et al. 2014

2014 9th International Design and Test Symposium (IDT)

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This paper addresses the problem of optimal hardware-realization of finite-word-length (FWL) linear controllers dedicated to MEMS applications. The biggest challenge is to ensure satisfactory control performances with a minimal hardware. To come up, two distinct but complementary optimizations can be undertaken: in control theory and in binary arithmetic. Only the latter is involved in this work. Because MEMS applications are targeted, the binary arithmetic must be fast enough to cope with the rapid dynamic of MEMS; powerefficient for an embedded control; highly scalable for an easy adjustment of the control performances; and easily predictable to provide a precise idea on the required logic resources before the implementation. The exploration of a number of binary arithmetics showed that radix-2 r is the best candidate that fits the aforementioned requirements. It has been fully exploited to designing efficient multiplier cores, which are the real engine of the linear systems. The radix-2 r arithmetic was applied to the hardware integration of two FWL structures: a linear time variant PID controller and a linear time invariant LQG controller with Kalman filtering. Both controllers showed a clear superiority over their existing counterparts, or in comparison to their initial non-optimized forms.

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Section: Our Contribution In the Binary Arithmeticmentioning

confidence: 99%

A new binary arithmetic for finite-word-length linear controllers: MEMS applications

Oudjida

Liacha

Berrandjia

et al. 2014

2014 9th International Design and Test Symposium (IDT)

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show abstract

“…For that, we considered two discrete forms of PID algorithm: the commercial form [22], called also the standard or ISA form, and the incremental form. These two forms went through three successive types of FPGA implementations, using: Booth multiplication algorithm (BMA) [23], modified Booth multiplication algorithm (MBMA) [24], and a new developed version called recursive multibit recoding multiplication algorithm (RMRMA) [25]. Results show gradual improvements with clear superiority over those provided in [21].…”

Section: Background and Motivationmentioning

confidence: 99%

“…This would not have been possible without the use of the new highly serialisable multi-bit multiplication algorithm (equation 13). The incorporation of equation (13) [25] into equations (1) and (2) as an efficient PID engine, allows the generation of PID architectures classified as regular iterative architectures (RIA) [44], known for their high conformity with the principles of regularity and locality. In addition to equation (13), we propose in [25] several new highly serialisable multiplication algorithms, offering different features in power, space and delay, depending on the operand size (n).…”

mentioning

confidence: 99%

Design of high-speed and low-power finite-word-length PID controllers

Oudjida

Chaillet

Liacha

et al. 2014

Control Theory Technol.

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“…In our preceding work [20], we pursued this combination process farther and generated a series of higher radix (2 . However, what still remains unknown is to determine, for a given N value, the proper radix (2 r ) that leads to the optimal architecture.…”

Section: B Our New Radix-2 16 Recodingmentioning

confidence: 99%

A New High Radix-2r (r ≥ 8) Multibit Recoding Algorithm for Large Operand Size (N ≥ 32) Multipliers

Oudjida¹,

Chaillet²,

Berrandjia³

et al. 2013

Journal of Low Power Electronics

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A New Recursive Multibit Recoding Algorithm for High-Speed and Low-Power Multiplier

Cited by 10 publications

References 13 publications

A new binary arithmetic for finite-word-length linear controllers: MEMS applications

A new binary arithmetic for finite-word-length linear controllers: MEMS applications

Design of high-speed and low-power finite-word-length PID controllers

A New High Radix-2<SUP>r</SUP> (<I>r</I> ≥ 8) Multibit Recoding Algorithm for Large Operand Size (<I>N</I> ≥ 32) Multipliers

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