This paper presents the device-technological simulation of local 3D SOI structures. These structures are created by use microcavities under surface of silicon wafer. Is shown that proposed microcavities could be use as a constructive material for CMOS transistor array on the bulk silicon and 3D SOI-CMOS transistor array, as well as the sensitive elements and their combinations. Such structures allow creation and monolithic integration the CMOS, SOI-CMOS circuits and sensitive elements for IC and SoC.