High SCR Design for One-Transistor Split-Gate Full-Featured EEPROM

Abstract

A high source-coupling ratio design for full-featured EEPROM composed of one-transistor split-gate cells with a cell area of less than 22 F 2 is proposed. This is in contrast to a traditional cell that requires an extra select transistor and is not area economic when compared to the new design cell. In this design, the cell adopts poly-poly Fowler-Nordheim tunneling to erase, and an inhibited source voltage is used for the unselected cell to achieve bit erase. It has demonstrated excellent program and erase disturb margins and passed 300 k program/erase (P/E) cycling test. It was found that after P/E cycling stress, the cell gains a better erase disturb immunity.

Novel vertical channel double gate structures for high density and low power flash memory applications

“…A schematic cross sectional view is shown in Figure 4. Compared with conventional planar split-gate flash cell [12,13] , the proposed VSAS-FG cell can achieve self-alignment of the split-gate channel and the floating-gate and can be realized without any additional mask. The proposed device can also have higher capability to shrink the cell area with better suppression of the short channel effects due to the little dependence of the cell area on the gate length.…”