High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory

A gate-all-around polycrystalline silicon nanowire (NW) floating-gate (FG) memory device was fabricated and characterized in this work. The cross-section of the NW channels was intentionally made to be triangular in shape in order to study the effects of the corners on the device operation. Our results indicate that the channel corners are effective in lowering the programming and erasing (P/E) operation voltages. As compared with the charge-trapping type devices, a larger memory window is obtained with the FG scheme under low-voltage P/E conditions. A model considering the nature of the charge storage medium is proposed to explain the above findings.

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Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

Dong

Kong

et al. 2010

J. Semicond.

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The erase voltage impact on the 0.18 m triple self-aligned split-gate flash endurance is studied. An optimized erase voltage is necessary in order to achieve the best endurance. A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop, which is induced by tunnel oxide charge trapping during program/erase cycling. A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping. A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.

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High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory

Cited by 4 publications

References 6 publications

The split-gate flash memory with an extra select gate for automotive applications

The split-gate flash memory with an extra select gate for automotive applications

Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire

Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

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