independent to CMOS gate oxide thickness and the critical A new gateless anti-fuse cell with 45nm CMOS fully design rules. By this feature, this cell is enabling to compatible process has been developed for advanced implement in advanced pure CMOS logic processes and programmable logic applications. This gateless anti-fuse platforms.cell processed by pure logic process and decoupled with logic gate oxide has a highly stable and five orders of on/off current window. It also exhibits superior program A. Physical Properties performance by only 5V operation with no more than 10AWith a small cell size of 1.3gm x 0.34gm, as show in programming current. This new nitride gateless anti-fuse Fig. l(b), the gateless anti-fuse (GAF) device decoupled cell is a very promising logic OTP solution with fully with transistor gate oxide thickness is enabling a high CMOS compatible process below 90nm node. density of data storage application. This anti-fuse cell consists of a p-channel select transistor in series with a
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