High Resolution FPGA DPWM Based on Variable Clock Phase Shifting

Castro, Ángel de; Todorovich, Elías

doi:10.1109/tpel.2009.2037818

Cited by 44 publications

(11 citation statements)

References 18 publications

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“…A DCMbased DPWM with 2.5 ns resolution was proposed in [5], but it requires a considerable amount of additional logic and manual placement effort. A similar approach in [6] achieved under 20 ps resolution, which is the highest resolution reported to date. However, it requires a high performance DCM which may not be present in general-purpose FPGAs, and it also relies on the update time of the DCM phase-shift command, thus limiting its applicability.…”

Section: Introductionmentioning

confidence: 73%

Simple Digital Pulse Width Modulator with 60 picoseconds resolution using a low-cost FPGA

Costinett

Rodrı́guez

Maksimović

2012

2012 15th International Power Electronics and Motion Control Conference (EPE/PEMC)

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This paper describes a very simple Digital Pulse Width Modulator (DPWM), with under 100 picoseconds resolution capability in low-cost field-programmable gate arrays (FPGA). The DPWM implementation is based on internal carry chains and internal logic resources which are present in most FPGA families. The proposed approach does not require manual routing or placement, consumes few hardware resources, and does not rely on specialized phase locked loop or clock management resources. The DPWM is capable of supporting high switching frequencies for digitally controlled switched-mode power converters. A 50 MHz switching frequency DPWM with 60 picoseconds resolution and a 1 MHz switching frequency DPWM with 90 picoseconds resolution are experimentally demonstrated, with monotonicity and excellent linearity.

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Section: Introductionmentioning

confidence: 73%

Simple Digital Pulse Width Modulator with 60 picoseconds resolution using a low-cost FPGA

Costinett

Rodrı́guez

Maksimović

2012

2012 15th International Power Electronics and Motion Control Conference (EPE/PEMC)

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“…DCM block is utilized to shift the phase of clocks in small increments. The resolution obtained by this method is greater than the traditional methods with a drawback of delay in phase shift update time [10]. Hybrid DPWM architecture utilizing the DCM block along with comparator and counter is proposed [5] [11].…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based High-Frequency Digital Pulse Width Modulator Architecture for DC-DC Converters

Radhika¹,

Baskaran²

2016

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Digital pulse width modulator is an integral part in digitally controlled Direct Current to Direct Current (DC-DC) converter utilized in modern portable devices. This paper presents a new Digital Pulse Width Modulator (DPWM) architecture for DC-DC converter using mealy finite state machine with gray code encoding scheme and one hot encoding method to derive the variable duty cycle Pulse Width Modulation (PWM) signal without varying the clock frequency. To verify the proposed DPWM technique, the architecture with control input of six, five and four bits are implemented and the maximum operating frequency along with power consumption results is obtained for different Field Programmable Gate Array (FPGA) devices. The post layout timing results are presented showing that architecture can work with maximum frequency of 326 MHz and derive PWM signal of 3.59 MHz. Experimental results show the implementation of the proposed architecture in low-cost FPGA (Spartan 3A) with on-board oscillator clock frequency of 12 MHz which is multiplied internally by two with Digital Clock Manager (DCM) and derive the PWM signal of 1.5 MHz with a time resolution of 1 ps.

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“…FPGA technology offers shorter design cycle, much faster computation speed, reduced cost, less-complex circuitry and convenient application in algorithm modification. FPGA-based digital controllers have been successfully used in applications such as PWM inverters [4], multilevel converters [5], power-factor correction [6], and electrical-machine control [7].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of FPGA based high resolution digital pulse width modulator

Sabarinath¹,

Sivanandam²

2013

2013 International Conference on Communication and Signal Processing

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Advantages and recent developments of digital control have led to an increasing use of digital pulse width modulators. The resolution of the digital pulse width modulator determines the accuracy in the output current/voltage. So resolution has direct influence in the performance of the system. This paper presents three architectures to improve the resolution of the digital pulse width modulator. Among these two architectures are based on the DCM (Digital Clock Manager) block and the other one is based on the IODELAYE1(I/O Delay Element) available in the VIRTEX-6 FPGA. These architectures are designed, implemented and compared to analyze the performance.Index Terms-Digital clock manager, Field programmable gate array(FPGA), IODELAYE1, pulse width modulator.

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High Resolution FPGA DPWM Based on Variable Clock Phase Shifting

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Cited by 44 publications

References 18 publications

Simple Digital Pulse Width Modulator with 60 picoseconds resolution using a low-cost FPGA

Simple Digital Pulse Width Modulator with 60 picoseconds resolution using a low-cost FPGA

FPGA-Based High-Frequency Digital Pulse Width Modulator Architecture for DC-DC Converters

Design and implementation of FPGA based high resolution digital pulse width modulator

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