In many application Floating point Arithmetic is basic building blocks such as Scientific, digital signal processing and numeric. In this Floating point Arithmetic, Multiplication is most commonly used method. This multipliers are going to discussing about the double precision multiplier. This double precision operation is performed in the form of IEEE-754 FP (floating point) standard format. The first architecture is the novel truncated block multiplication, with one unit in the last place (ULP) precision from IEEE-754 FP standard format. The second architecture is used to regain the lost of accuracy from the first design with some extra hardware logic. The third architecture is used to perform either single precision or double precision. The Vedic multiplication algorithm is used in all the architecture for the purpose of multiplication process.
Advantages and recent developments of digital control have led to an increasing use of digital pulse width modulators. The resolution of the digital pulse width modulator determines the accuracy in the output current/voltage. So resolution has direct influence in the performance of the system. This paper presents three architectures to improve the resolution of the digital pulse width modulator. Among these two architectures are based on the DCM (Digital Clock Manager) block and the other one is based on the IODELAYE1(I/O Delay Element) available in the VIRTEX-6 FPGA. These architectures are designed, implemented and compared to analyze the performance.Index Terms-Digital clock manager, Field programmable gate array(FPGA), IODELAYE1, pulse width modulator.
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