Simple Digital Pulse Width Modulator with 60 picoseconds resolution using a low-cost FPGA

Costinett, Daniel; Rodrı́guez, Miguel A.; Maksimović, Dragan

doi:10.1109/epepemc.2012.6397402

Cited by 7 publications

(4 citation statements)

References 14 publications

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“…Estado de la técnica DPWM l aumento de la frecuencia de conmutación en los circuitos electrónicos ha ido evolucionando a lo largo de los años. Inicialmente, los primeros moduladores digitales generaban las distintas modulaciones a través de la combinación de contadores y comparadores [8], [9]. Para la modulación de tipo PWM, el contador es encargado de generar la señal triangular usando para ello el reloj del dispositivo controlador como referencia temporal.…”

Section: Estructura De La Tesisunclassified

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Design and Implementation of Two Hybrid High Frequency DPWMs Using Delay Blocks on FPGAs

Fernandez-Gomez

Sanchez²,

Castro³

et al. 2021

IEEE Trans. Power Electron.

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Section: Estructura De La Tesisunclassified

“…En [8], los autores proponen dos diseños de arquitectura DPWM de tipo híbrido, donde la parte asíncrona está formada por una línea de retardo que ellos mismos diseñan utilizando puertas lógicas existentes dentro de la propia lógica de la FPGA. Estas arquitecturas fueron probadas en dos modelos de FPGAs distintos.…”

Section: Uso De Arquitecturas Híbridasunclassified

Design and Implementation of Two Hybrid High Frequency DPWMs Using Delay Blocks on FPGAs

Fernandez-Gomez

Sanchez²,

Castro³

et al. 2021

IEEE Trans. Power Electron.

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“…Finally, the blue cluster shows that the fault tolerance and high reliability systems are based in fault injection impelmentations [1488,1489] and single event upset tolerance mechanisms [1490][1491][1492]. In addition, other relevant relations are shown in colored lines, like digital control with PWM [1493,1494], simulation with modeling [1057,1118,1495] and performance with algorithms [1496][1497][1498].…”

Section: Applications Mappingmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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“…These implementations obtain excellent resolution results, but they require manual routing or post fitting adjustments, and they lack of flexibility as the obtained resolution must be a multiple of technology dependent delays. A recent work [7] uses Altera's synthesis tool features to avoid the need for manual routing but still suffer from the second drawback.…”

Section: Introductionmentioning

confidence: 99%

Analysis and implementation of low-cost FPGA-based digital pulse-width modulators

Leon¹,

Sotta²,

Eirea³

et al. 2014

2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings

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This paper describes the architecture and operating principles of two digital pulse-width modulator (DPWM) implementations for low-cost field-programmable gate arrays (FPGAs). Both architectures are based on a countercomparator block to process the most significant bits (MSB) portion of the reference input, enriched with additional elements to enhance duty-cycle resolution according to the less significant bits (LSB). The first architecture described has already been reported, it uses the on-chip PLL blocks to generate fixed delays and a selector to choose the one corresponding with the desired duty-cycle. Post-fitting adjustment of PLL delays are required to compensate delay differences between the diverse signal paths across the selector. In the second architecture described, a serializer-deserializer (SERDES) module is used to serialize a thermometer-coded representation of the LSB portion of the input. This serialization technique is commonly used for data transmission on high-speed serial I/O data transmission standards like LVDS and is extensively supported by FPGA providers. Experimental results are presented for both architectures synthesized on standard low-cost FPGA chips, showing very good linearity and resolutions up to 1ns. The first architecture provides a moderately better resolution. The second architecture, on the other hand, is a much more robust solution as it requires no post-fitting delay adjustments.

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Simple Digital Pulse Width Modulator with 60 picoseconds resolution using a low-cost FPGA

Cited by 7 publications

References 14 publications

Design and Implementation of Two Hybrid High Frequency DPWMs Using Delay Blocks on FPGAs

Design and Implementation of Two Hybrid High Frequency DPWMs Using Delay Blocks on FPGAs

Field Programmable Gate Array Applications—A Scientometric Review

Analysis and implementation of low-cost FPGA-based digital pulse-width modulators

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