High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications

Stefo, Riad; Schreiter, Jörg; Schlussler, J.-U.; Schüffny, René

doi:10.1109/fpt.2003.1275728

Cited by 9 publications

(6 citation statements)

References 6 publications

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“…The number of bits in the control word L could be modified to get extended frequency range, thereby portability is achieved. Therefore L value is set for synthesise flow, so that portability is achieved by only changing the L value for different frequencies which is also technology independent (Stefo et al 2003). …”

Section: Ring Oscillatormentioning

confidence: 99%

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Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

Moorthi

Meganathan

Janarthanan

et al. 2009

International Journal of Electronics

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An efficient architecture for a low jitter all digital phase locked loop (ADPLL) suitable for high speed system-on-chip (SoC) applications is presented in this article. The ADPLL is designed using standard cells and described by hardware description language. The ADPLL implemented in a 90-nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that the PLL has a cycle to cycle jitter of 164 ps at 100 MHz. Because the digitally controlled oscillator can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for SoC applications.Keywords: all digital phase locked loop (ADPLL); system-on-chip (SoC); phase locked loop (PLL); very high speed integrated circuit (VHSIC); hardware description language (VHDL); digitally controlled oscillator (DCO); phase frequency detector (PFD); voltage controlled oscillator (VCO)

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Section: Ring Oscillatormentioning

confidence: 99%

“…The oscillator is implemented as a ring oscillator with one NAND-gate (Stefo, Schreiter, Schlussler and Schuffny 2003) as inverter and with variable delay elements as shown in Figure 4. The NAND-gate is to enable power down by shutting down the oscillator.…”

Section: Ring Oscillatormentioning

confidence: 99%

Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

Moorthi

Meganathan

Janarthanan

et al. 2009

International Journal of Electronics

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“…fast and easy way as a typical IP core in every standard digital synthesis-based design flow. This is realized by a combination of the standard-cell based low jitter DCO presented in [3,5] and a robust frequency regulation algorithm based on successive approximation, as described in the following.…”

Section: Introductionmentioning

confidence: 99%

A programmable clock generator HDL softcore

Eisenreich

Mayr

Henker

et al. 2007

2007 50th Midwest Symposium on Circuits and Systems

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This paper presents a hardware implementation of a fully synthesizable, technology independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a deflined lock-in time of at most 8 reference cycles. ASICs in CMOS AMS O,35um and UMC O,l3um have been manufactured and tested. Measurements show competitive results to state-of-theart mixed signal implementations.

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“…It consumes very less power. ADPLL can be used in clock distribution and generation for processors [4]. The first ADPLL was reported in 1980 [12] .With use of 74HC297 IC [3] a modified form of ADPLL is developed.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of ADPLL with Ripple Reduction Techniques

Kumar¹

2012

VLSICS

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In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

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High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications

Cited by 9 publications

References 6 publications

Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

A programmable clock generator HDL softcore

FPGA Implementation of ADPLL with Ripple Reduction Techniques

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