FPGA Implementation of ADPLL with Ripple Reduction Techniques

Abstract

In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

Firmware implementation and experimental research of the phase-locked loop with improved noise immunity

“…In particular, [10] provides a detailed classification of digital PLLs and the work [11] gives the options of the PLL key component's implementation depending on their type. In modern worldwide technical literature, a lot of attention is devoted to the research of the PLL with non-uniform sampling techniques, which work with pulse signals, and their practical implementation for clock formation [12] or frequency synthesis with low phase noise [13]. The work [14] evaluates the phase noise of the signal at the device output under the influence of a noise signal at the device input for two types of such devices.…”