Firmware implementation and experimental research of the phase-locked loop with improved noise immunity

Bondariev, Andriy; Altunin, Serhii; Horbatyi, Ivan; Maksymiv, Ivan

doi:10.15587/1729-4061.2018.143178

Cited by 9 publications

(6 citation statements)

References 7 publications

(11 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The AMMC demodulator comprises generator 1 of harmonic carrier oscillation synchronized by frequency and phase with the oscillation of generator of harmonic carrier oscillation of transmission, from first to N th phase shifters 2-4 for angles n  , from first to N th multipliers 5-7, from first to N th low pass filters 8-10 and a data shaper 11 having N inputs. The AMMC demodulator includes the phase-locked loop (PLL), which can be constructed on the basis of known or new proposed methods and devices of phase synchronization [12].…”

Section: Varieties Of Modulationmentioning

confidence: 99%

International Journal of Electronics and Telecommunications

Horbatyi

Yashchyshyn

2020

View full text Add to dashboard Cite

It is proposed to modernize the DVB-S2 standard by using AMMC (amplitude modulation of many components) signals instead of 8PSK (8-phase shift keying) and APSK (amplitude-phase shift keying) signals, and to modernize the DVB-S2 standard equipment by using the AMMC modulator and AMMC demodulator. Usage of AMMC makes it possible to reduce the symbol error rate in communication channel up to 52 times. The satellite digital video broadcast systems that apply signal-code constructions based on AMMC are characterized by a higher energy efficiency from 1 to 2.6 dB compared with signalcode constructions based on 8PSK and APSK.

show abstract

Section: Varieties Of Modulationmentioning

confidence: 99%

International Journal of Electronics and Telecommunications

Horbatyi

Yashchyshyn

2020

View full text Add to dashboard Cite

show abstract

“…The influence of the modified PD on the PLL dynamic behavior has already been investigated in [12]. However, the above-mentioned study was conducted under the noise-free conditions.…”

Section: Experimental Study Of the Pll Dynamic Behavior Under The Inf...mentioning

confidence: 99%

“…In the above mentioned works, the object of the study was the analog PLL, and the research methods were limited to the simulation. The described above studies were improved in work [12], which presents a firmware implemented PLL with high noise immunity and experimental investigations of its boundary noise immunity. The results of the study show that the digital PLL (created according to the analog prototype) with a modified phase detector has a lower noise threshold of up to 2.5 dB and has better dynamic properties comparing to the classical PLL.…”

Section: Introductionmentioning

confidence: 99%

“…These parameters determine the hold-in range of the device [14,15] and affect the form of the PLL frequency response [13]. [12]. Fig.…”

Section: Introductionmentioning

confidence: 99%

“…This is possible if the coefficients of proportionality of the two filters are the same and their cutoff frequencies are determined by the ratio f HPF = f NBF / m 0 . The mathematical model of such a device is described in detail in [12].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Simulation and investigations of a software implemented phase-locked loop with improved noise immunity

Bondariev,

Maksymiv,

Altunin

2018

Comput. probl. electr. eng.

Self Cite

View full text Add to dashboard Cite

The improvement of noise immunity of a communication system is an effective way to increase the capacity of communication systems, which would provide more qualitative service for a larger number of users. This task can be solved by lowering the noise threshold of a phase-locked loop (PLL) in these systems if the dynamic properties of the device are preserved. The literature review indicates that such a device with improved noise immunity has already been implemented, but the effects of noise and modulation on its dynamic behavior were analyzed separately. This article is devoted to the analysis of the behavior of a digital firmware PLL under the simultaneous influence of noise and modulation of the input signal. The article depicts the structure of the classical digital PLL and its modifications and explains key differences between them. The simulation of the classical PLL with either absence or presence of noise at the device input was carried out. The simulation results show that the PLL is not able to detect all phase changes when the noise is present. Besides, the modified PLL has a wider working frequency range than the classical one under noisy conditions. The investigations of the PLL dynamic behavior with the simultaneous influence of random noise and Binary Phase Shift Keying (BPSK) modulated input signal was performed. The results of the research show that the duration of the transient processes during the processing of the BPSK modulated signal in the modified device is at least twice as low as that for the classical one. In addition, the number of errors during the signal detection increases faster for the classical PLL than for the modified one when the noise level rises. The use of the modified PLL in modern communication systems gives an opportunity to increase their capacity.

show abstract