2007 50th Midwest Symposium on Circuits and Systems 2007
DOI: 10.1109/mwscas.2007.4488528
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A programmable clock generator HDL softcore

Abstract: This paper presents a hardware implementation of a fully synthesizable, technology independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a deflined lock-in time of at most 8 reference cycles. ASICs in CMOS AMS O,35um and UMC O,l3um have been manufactured and tested. Measurements show competitive result… Show more

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Cited by 3 publications
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“…The ADPLLs in [5][6][7][8][9][10] designed based on binary searching and Time to Digital Converter (TDC). These designs have higher resolution and less sensitivity to noise, but the additional circuits raised more power consumption.…”
Section: Introductionmentioning
confidence: 99%
“…The ADPLLs in [5][6][7][8][9][10] designed based on binary searching and Time to Digital Converter (TDC). These designs have higher resolution and less sensitivity to noise, but the additional circuits raised more power consumption.…”
Section: Introductionmentioning
confidence: 99%