Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

Moorthi, S.; Meganathan, D.; Janarthanan, D; Kumar, P. Praveen; Perinbam, J. Raja Paul

doi:10.1080/00207210903017255

Cited by 8 publications

(6 citation statements)

References 5 publications

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“…It selects different timing paths in order to increase or decrease the loop delay of a ring oscillator as published by D. Sheng et al in [11]. As a stand-alone approach, this results in a wide frequency range with a low resolution that leads to a large cycle to cycle jitter.…”

Section: A High Frequency Dcosmentioning

confidence: 94%

Embedded low power clock generator for sensor nodes

Schrape

Vater

2012

Norchip 2012

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In this paper an embedded clock generation solution for low power sensor nodes is presented. A design example of a Digitally Controlled Oscillator (DCO) is given and compared to other approaches. The paper discusses the most common clock architectures for sensor nodes, their design challenges and potential integration issues. The proposed DCO is adjustable to 64 different frequencies in the range of 5.8 MHz to 13.9 MHz fed by a 2.5 V voltage supply. With an area utilization of 0.024 mm 2 in a 0.25 µm SiGe BiCMOS process, and an average current consumption of less than 106 µA, it fits best into power-area trade off for an internal several-MHz clock generator. It is designed as an IP-Core and can be placed directly into the digital core of a sensor node. Due to its robustness, the DCO can be connected to the noisy digital voltage supply. A test chip was sent to fabrication.

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Section: A High Frequency Dcosmentioning

confidence: 94%

Embedded low power clock generator for sensor nodes

Schrape

Vater

2012

Norchip 2012

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“…This component has three different tuning stages. The first one, the coarse tuning stage, is a slight modification of the selectable inverter chain proposed by S. Moorthi et al in [5]. To achieve a wider frequency range the used standard cells need to have a short gate delay.…”

Section: Digitally Controlled Oscillatormentioning

confidence: 99%

“…Therefore, a selectable inverter chain as published by S. Moorthi et al in [5] provides a wide operating range. In order to achieve a high resolution one can use a ring oscillator with parallel connected tri-state inverters as announced by T. Olsson et al in [8].…”

Section: Introductionmentioning

confidence: 97%

An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis

Schrape

Winkler

Zeidler

et al. 2011

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

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Abstract. In this paper an All-Digital Phase-Locked Loop (ADPLL) with a high resolution and a wide frequency range for local on-chip clock generation is described. The proposed ADPLL has an operating range from 250 MHz to 1.3 GHz and a resolution of 25 ps. In contrast to other designs, the Digitally Controlled Oscillator (DCO) combines three different development approaches to achieve the desired performance. The ADPLL provides four different algorithms to control the DCO. Depending on the selected algorithm and the desired frequency, the lock-in time varies between 54 to more than hundreds reference cycles. The output of the synthesized clock is directly connected to a Low Voltage Differential Signaling (LVDS) interface to provide a high frequency LVDS clock. Before their VHDL implementation, all components were simulated using an event driven Matlab model. This proposed ADPLL uses standard cell library elements only and is implemented in an IHP 0.25 µm BiCMOS process. The overall power dissipation is less than 50 mW (@ 800 MHz) with a 2.5 V power supply. Due to its VHDL description the design can be ported to other processes in short development time.

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“…This gives very good phase a frequency error tracking that was not implemented with 74HC297 IC. Clock recovery is most important use of ADPLL [7]. Data may affect with noise that noise is called ripple.…”

Section: Introductionmentioning

confidence: 99%

“…Data may affect with noise that noise is called ripple. For reducing ripple in the ADPLL circuit ripple reduction techniques are also reported in different research papers [1], [9], [10], [11].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of ADPLL with Ripple Reduction Techniques

Kumar¹

2012

VLSICS

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In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

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Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

Cited by 8 publications

References 5 publications

Embedded low power clock generator for sensor nodes

Embedded low power clock generator for sensor nodes

An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis

FPGA Implementation of ADPLL with Ripple Reduction Techniques

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