High-radix systolic modular multiplication on reconfigurable hardware

McIvor, C.; McLoone, M.; McCanny, J.V.

doi:10.1109/fpt.2005.1568518

Cited by 20 publications

(24 citation statements)

References 16 publications

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“…In fact, this is a common barrier in the high-radix Montgomery algorithm implementations: the quotient is hard to generate in a single clock cycle. This barrier also exists in other systolic high-radix designs [9,22].…”

Section: High-radix Montgomery Multiplicationmentioning

confidence: 99%

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A High-Speed Elliptic Curve Cryptographic Processor for Generic Curves over $$\mathrm{GF}(p)$$

Liu

Pan

et al. 2014

Lecture Notes in Computer Science

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Abstract. Elliptic curve cryptography (ECC) is preferred for highspeed applications due to the lower computational complexity compared with other public-key cryptographic schemes. As the basic arithmetic, the modular multiplication is the most time-consuming operation in publickey cryptosystems. The existing high-radix Montgomery multipliers performed a single Montgomery multiplication either in approximately 2n clock cycles, or approximately n cycles but with a very low frequency, where n is the number of words. In this paper, we first design a novel Montgomery multiplier by combining a quotient pipelining Montgomery multiplication algorithm with a parallel array design. The parallel design with one-way carry propagation can determine the quotients in one clock cycle, thus one Montgomery multiplication can be completed in approximately n clock cycles. Meanwhile, by the quotient pipelining technique applied in digital signal processing (DSP) blocks, our multiplier works in a high frequency. We also implement an ECC processor for generic curves over GF(p) using the novel multiplier on FPGAs. To the best of our knowledge, our processor is the fastest among the existing ECC implementations over GF(p).

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Section: High-radix Montgomery Multiplicationmentioning

confidence: 99%

“…From the perspective of the radix, the Montgomery multiplication implementations can be divided into two categories: radix-2 based [7,21] and high-radix based [1,2,9,11,17,19,20,22,23]. Compared with the former one, the latter, which can significantly reduce the required clock cycles, are preferred for high-speed applications.…”

Section: Introductionmentioning

confidence: 99%

A High-Speed Elliptic Curve Cryptographic Processor for Generic Curves over $$\mathrm{GF}(p)$$

Liu

Pan

et al. 2014

Lecture Notes in Computer Science

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“…This feature makes the implementation expensive. The systolic high-radix design by McIvor et al described in [13] is also capable of very high speed operation, but suffers from the same disadvantage of large area requirements for fast multiplier units. A different approach based on processing multi-precision operands in carry-save form has been presented in [14].…”

Section: Introductionmentioning

confidence: 99%

New Hardware Architectures for Montgomery Modular Multiplication Algorithm

Huang

Gaj

El‐Ghazawi

2011

IEEE Trans. Comput.

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Abstract-Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koç proposed the Multiple-Word Radix-2 Montgomery Multiplication (MWR2MM) algorithm and introduced a now-classic architecture for implementing Montgomery multiplication in hardware. With parameters optimized for minimum latency, this architecture performs a single Montgomery multiplication in approximately 2n clock cycles, where n is the size of operands in bits. In this paper we propose two new hardware architectures that are able to perform the same operation in approximately n clock cycles with almost the same clock period. These two architectures are based on pre-computing partial results using two possible assumptions regarding the most significant bit of the previous word. These two architectures outperform the original architecture of Tenca and Koç in terms of the product latency times area by 23% and 50%, respectively, for several most common operand sizes used in cryptography. The architecture in radix-2 can be extended to the case of radix-4, while preserving a factor of two speed-up over the corresponding radix-4 design by Tenca, Todorov, and Koç from CHES 2001. Our optimization has been verified by modeling it using Verilog-HDL, implementing it on Xilinx Virtex-II 6000 FPGA, and experimentally testing it using SRC-6 reconfigurable computer.

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“…MWRkMM algorithm requires the built-in multipliers to speed up the computation and this feature makes the implementation expensive. The systolic high-radix design by McIvor et al described in [10] is also capable of very high speed operation, but suffers from the same disadvantage of large requirements for fast multiplier units. A different approach based on processing multi-precision operands in carry-save form has been presented in [11].…”

Section: Introductionmentioning

confidence: 99%

An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm

Huang

Gaj

Kwon

et al.

Public Key Cryptography – PKC 2008

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Abstract. Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koç introduced a now-classical architecture for implementing Montgomery multiplication in hardware. With parameters optimized for minimum latency, this architecture performs a single Montgomery multiplication in approximately 2n clock cycles, where n is the size of operands in bits. In this paper we propose and discuss an optimized hardware architecture performing the same operation in approximately n clock cycles with almost the same clock period. Our architecture is based on pre-computing partial results using two possible assumptions regarding the most significant bit of the previous word, and is only marginally more demanding in terms of the circuit area. The new radix-2 architecture can be extended for the case of radix-4, while preserving a factor of two speed-up over the corresponding radix-4 design by Tenca, Todorov, and Koç from CHES 2001. Our architecture has been verified by modeling it in Verilog-HDL, implementing it using Xilinx Virtex-II 6000 FPGA, and experimentally testing it using SRC-6 reconfigurable computer.

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High-radix systolic modular multiplication on reconfigurable hardware

Cited by 20 publications

References 16 publications

A High-Speed Elliptic Curve Cryptographic Processor for Generic Curves over $$\mathrm{GF}(p)$$

A High-Speed Elliptic Curve Cryptographic Processor for Generic Curves over $$\mathrm{GF}(p)$$

New Hardware Architectures for Montgomery Modular Multiplication Algorithm

An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm

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