A High-Speed Elliptic Curve Cryptographic Processor for Generic Curves over $$\mathrm{GF}(p)$$

Ma, Yuan; Liu, Zongbin; Pan, Wuqiong; Jing, Jiwu

doi:10.1007/978-3-662-43414-7_21

Cited by 15 publications

(31 citation statements)

References 22 publications

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“…We obtained very close results for both area and timing: e.g. 37 DSP blocks for 256-bit F P for us and [6].…”

Section: Implementation and Comparisonsmentioning

confidence: 55%

“…This reduces circuit efficiency with lower utilization of DSP blocks. In [6], Ma et al proposed a MMM implementation based on Orup algorithm [7]. This implementation is known to be one of the fastest FPGA implementations.…”

Section: Background On F P Finite Field Multipliersmentioning

confidence: 99%

“…We implemented MM from [6] to help comparisons on the target FPGAs. We obtained very close results for both area and timing: e.g.…”

Section: Implementation and Comparisonsmentioning

confidence: 99%

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Hyper-threaded multiplier for HECC

Gallin

Tisserand

2017

2017 51st Asilomar Conference on Signals, Systems, and Computers

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Abstract-Modular multiplication is the most costly and common operation in hyper-elliptic curve cryptography. Over prime fields, it uses dependent partial products and reduction steps. These dependencies make FPGA implementations with fully pipelined DSP blocks difficult to optimize. We propose a new multiplier architecture with hyper-threaded capabilities. Several independent multiplications are handled in parallel for efficiently filling the pipeline and overlapping internal latencies by independent computations. It increases the silicon efficiency and leads to a better area / computation time trade-off than current state of the art. We use this hyper-threaded multiplier into small accelerators for hyper-elliptic curve cryptography in embedded systems.

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“…We obtained very close results for both area and timing: e.g. 37 DSP blocks for 256-bit F P for us and [6].…”

Section: Implementation and Comparisonsmentioning

confidence: 55%

Section: Background On F P Finite Field Multipliersmentioning

confidence: 99%

See 1 more Smart Citation

Hyper-threaded multiplier for HECC

Gallin

Tisserand

2017

2017 51st Asilomar Conference on Signals, Systems, and Computers

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“…Other works [1,20,36,19,29,27] outperform our architecture in terms of speed, but use a much larger number of embedded multipliers. Also, implementations only focusing on NIST curves are able to use the special prime shape, yielding a significant speed-up.…”

Section: Comparisonmentioning

confidence: 97%

Implementing Complete Formulas on Weierstrass Curves in Hardware

Massolino¹,

Renes²,

Batina³

2016

Security, Privacy, and Applied Cryptography Engineering

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Abstract. This work revisits the recent complete addition formulas for prime order elliptic curves of Renes, Costello and Batina in light of parallelization. We introduce the first hardware implementation of the new formulas on an FPGA based on three arithmetic units performing Montgomery multiplication. Our results are competitive with current literature and show the potential of the new complete formulas in hardware design. Furthermore, we present algorithms to compute the formulas using anywhere between two and six processors, using the minimum number of parallel field multiplications.

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“…Using the property of the pseudo-Mersenne value, this implementation can be specialized to run at high frequency and quickly computing the multiplication scalar. (iii) Third design is based on fast quotient pipelining Montgomery multiplication algorithm in [7]. The scalar multiplication algorithm is based on window method algorithm.…”

Section: Comparisonmentioning

confidence: 99%

Double Level Montgomery Cox-Rower Architecture, New Bounds

Bajard

Merkiche²

2015

Smart Card Research and Advanced Applications

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Abstract. Recently, the Residue Number System and the Cox-Rower architecture have been used to compute efficiently Elliptic Curve Cryptography over FPGA. In this paper, we are rewriting the conditions of Kawamura's theorem for the base extension without error in order to define the maximal range of the set from which the moduli can be chosen to build a base. At the same time, we give a procedure to compute correctly the truncation function of the Cox module. We also present a modified ALU of the Rower architecture using a second level of Montgomery Representation. Such architecture allows us to select the moduli with the new upper bound defined with the condition. This modification makes the Cox-Rower architecture suitable to compute 521 bits ECC with radix downto 16 bits compared to 18 with the classical Cox-Rower architecture. We validate our results through FPGA implementation of a scalar multiplication at classical cryptography security levels (NIST curves). Our implementation uses 35% less LUTs compared to the state of the art generic implementation of ECC using RNS for the same performance [5]. We also slightly improve the computation time (latency) and our implementation shows best ratio throughput/area for RNS computation supporting any curve independently of the chosen base.

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A High-Speed Elliptic Curve Cryptographic Processor for Generic Curves over $$\mathrm{GF}(p)$$

Cited by 15 publications

References 22 publications

Hyper-threaded multiplier for HECC

Hyper-threaded multiplier for HECC

Implementing Complete Formulas on Weierstrass Curves in Hardware

Double Level Montgomery Cox-Rower Architecture, New Bounds

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