An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm

Abstract

Abstract. Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koç introduced a now-classical architecture for implementing Montgomery multiplication in hardware. With parameters optimized for minimum latency, this architecture performs a single Montgomery multiplication in approximately 2n clock cycles, where n is the size of operands in bits. In this paper we propose and discuss an optimized hardware architecture performing the same operation in approximately n clock cycles with almost the same clock period. Our architecture is based on pre-computing partial results using two possible assumptions regarding the most significant bit of the previous word, and is only marginally more demanding in terms of the circuit area. The new radix-2 architecture can be extended for the case of radix-4, while preserving a factor of two speed-up over the corresponding radix-4 design by Tenca, Todorov, and Koç from CHES 2001. Our architecture has been verified by modeling it in Verilog-HDL, implementing it using Xilinx Virtex-II 6000 FPGA, and experimentally testing it using SRC-6 reconfigurable computer.

High-Performance Elliptic Curve Cryptography by Using the CIOS Method for Modular Multiplication

“…Its operations are described in Algorithm 6. 5 SOut ←LSW(t3) 6 return COut, SOut, m γ f cell Finally, the γ f cell terminate each γ cell chain. It consists in two additions as shown in Algorithm 7.…”

“…It's one of the most suitable algorithm for performing modular multiplications in hardware and software implementations. The efficient implementation of the Montgomery Modular Multiplication (MMM) in hardware was considered by many authors [3,6,7,18,19,23]. There is a variety of ways to perform the MMM, considering if multiplication and reduction are separated or integrated.…”

High Radix Montgomery Modular Multiplier on Modern FPGA

“…In their architecture, a single Montgomery multiplication is performed in approximately 2n clock cycles, where n is the size of operands in bits. At PKC 2008, Huang et al [2] proposed that of Tenca. The architecture performs a single Montgomery multiplication in approximately n clock cycles.…”

A modified radix-2 Montgomery modular multiplication with new recoding method

“…The radix-2 Montgomery method is based on an ingenious representation of the residue class modulo N, and replaces division by N operation with division by power of 2. However, there have been various attempts to improve its hardware implementations performance [2,3,4,5].…”