New Hardware Architectures for Montgomery Modular Multiplication Algorithm

Abstract

Abstract-Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koç proposed the Multiple-Word Radix-2 Montgomery Multiplication (MWR2MM) algorithm and introduced a now-classic architecture for implementing Montgomery multiplication in hardware. With parameters optimized for minimum latency, this architecture performs a single Montgomery multiplication in approximately 2n clock cycles, where n is the size of operands in bits. In this paper we propose two new hardware architectures that are able to perform the same operation in approximately n clock cycles with almost the same clock period. These two architectures are based on pre-computing partial results using two possible assumptions regarding the most significant bit of the previous word. These two architectures outperform the original architecture of Tenca and Koç in terms of the product latency times area by 23% and 50%, respectively, for several most common operand sizes used in cryptography. The architecture in radix-2 can be extended to the case of radix-4, while preserving a factor of two speed-up over the corresponding radix-4 design by Tenca, Todorov, and Koç from CHES 2001. Our optimization has been verified by modeling it using Verilog-HDL, implementing it on Xilinx Virtex-II 6000 FPGA, and experimentally testing it using SRC-6 reconfigurable computer.

High-Performance Elliptic Curve Cryptography by Using the CIOS Method for Modular Multiplication

“…In order to implement the modular Montgomery multiplication for fixed security level, we must choose the most suitable architecture. The results presented in this work are compared with the previous work [4,5,18,19] in the Table 3. We can notice that our results are better than [19] considering every point of comparison i.e.…”

“…Its operations are described in Algorithm 6. 5 SOut ←LSW(t3) 6 return COut, SOut, m γ f cell Finally, the γ f cell terminate each γ cell chain. It consists in two additions as shown in Algorithm 7.…”

Design and Evaluation of Novel Effective Montgomery Modular Multiplication Architecture

“…Therefore, this modular multiplication algorithm is timeconsuming algorithm [11,17]. To further improve the performance of Montgomery modular multiplication algorithm, several computational techniques and hardware implementation have been proposed such as [7,9,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27 ]. One of the efficient modular multiplication algorithms is KPartition Montgomery Modular Multiplication (KPM3) algorithm [7].…”

“…Although hardware implementation of the binary Montgomery modular multiplication is simple, but it is time-consuming operation. To improve the performance of Montgomery modular multiplication algorithm and architecture, several hardware implementation method and computational techniques have been developed that can be categories into four groups: using high-radix technique [11][12][13][14][15][16][17], using systolic array architecture [18][19][20], using carry-save addition architecture [11,16,21,22,23], and using scalable architecture [9,12,24,25,26,27].…”

Massively parallel modular exponentiation method and its implementation in software and hardware for high-performance cryptographic systems

“…In that implementation, high-radix Montgomery algorithm for MM is combined with a systolic array design and so allows for an efficient high radix ME. In [19], the authors propose a hardware architecture that is based on pre-computing partial results using speculation regarding the most significant bit handled data.…”