Massively parallel modular exponentiation method and its implementation in software and hardware for high-performance cryptographic systems

Abstract

Most cryptographic systems are based on modular exponentiation (ME). It is performed using successive modular multiplications (MMs). In this case, there are many ways to improve the throughput of a cryptographic system implementation: one is reducing the number of the required MMs and the other is reducing the time spent in performing a single MM and a third way consists of executing required independent modular multiplications (IMMs) in parallel. With the purpose of further accelerating the computation of ME, we investigate the impact of these three strategies. First, we propose a massively parallel scheme aiming at performing all IMMs concurrently. The scheme is based on the m-ary exponentiation method, which groups the exponent bits into partition so that the number of required MMs is reduced, provided that some common modular powers are pre-computed and stored for future repeated use. Finally, two different implementations for the MM are used: one is sequential and the other systolic. This investigation is culminated by a comparison of the speedups yielded against the extra-costs due for seven different implementations. One implementation is software based and the other six are hardware based.

Performance evaluation of M-ary algorithm using reprogrammable hardware

“…6. Creates a private key with the set (p, q, d) = (11,227,33) and a public key (n, e) = (2497, 137). Now, using ASCII code, "s" is represented with 83 as the message to transport to use the cipher and decipher steps.…”

“…Previous systems were made with different schemes, taking advantage of a pure hardware co-design approach (hardware subsystem and software subsystem) or using algorithms such as an addition-chain to reduce multiplication steps [7,11]. These systems were based on combining their best characteristics.…”