High quality InAs and GaSb thin layers grown on Si (111)

III–V compound semiconductor transistors—from planar to nanowire structures

“…106 Although vertical device fabrication may be regarded as more challenging than lateral device fabrication, important progress has been made and vertical III-V NW-FETs based on single or arrays of NWs fabricated by either epitaxial or etching techniques have been demonstrated (square symbols in Figure 5b ). Moreover, a modulation-doped GAA InGaAs NW-FET integrated on a Si substrate with excellent device properties 103 as well as vertical GAA InAs NW-FETs into which a thin InAs buffer layer had been introduced to reduce the access resistance toward the substrate 107 were recently demonstrated. Competitive radio frequency (RF) performance has been achieved, 108 and the fi rst RF circuits in the form of single-balanced down-conversion mixers operating up to 5 GHz were constructed.…”

Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

“…1a). The devices are fabricated on lowly p-doped Si {111} substrates with a 300-nm-thick epitaxially grown InAs layer [9]. InAs nanowires are grown in two types of arrays with nanowire center-to-center spacings of 200 nm and 500 nm, respectively, using metalorganic vapor phase epitaxy (MOVPE) where Au particles are used as seeds.…”

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

“…InAs nanowire MOSFETs are fabricated on lowly p-doped Si (111) substrates with an epitaxially grown InAs buffer layer [6]. The InAs layer serves both as a buffer layer for nanowire growth and as a low-resistive device bottom contact, avoiding transport over the InAs/Si heterojunction potential barrier [7].…”