Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

“…An organic second spacer is deposited and followed by the sputtering of the top metal electrode. More details of the fabrication method are found in [8].…”

“…However, in order to achieve a minimal resistive contribution of the access regions, a gate overlapping the contacts is needed. In this letter, vertical InAs nanowire MOSFETs fabricated using a self-aligned, gatelast process [8] are presented exhibiting excellent on-and off-state performance. The devices are studied by both DC and RF-characterization to evaluate the limiting contributions of the transistor design and the quality of the gate stack.…”

A Self-Aligned Gate-Last Process Applied to All-III–V CMOS on Si

“…Vertical nanowires with a gate-all-around (GAA) geometry is one alternative with beneficial performance at the 5 nm node [10]. The vertical nanowire geometry in particular decouples the gate length and contact geometry from the footprint area [11].…”

All-metal electrodes vertical gate-all-around device with self-catalyzed selective grown InAs NWs array

“…Semiconductor InAs NW is a promising alternative channel material in further high performance electronic devices because of its excellent electronic properties, such as high electron mobility, high electron injection velocity, small effective mass and easily formed ohmic contact with metals caused by Fermi level pinning near the bottom of its conductive band [11][12][13][14][15]. However, due to the complicated fabrication process of vertical gate-all-around (VGAA) FETs, only a few groups have reported the VGAA FETs based on InAs NWs [5,6,[16][17][18][19]. Using core-multishell NW channels, Hokkaido's group has realized VGAA transistors with subthreshold swing (SS) of 68 mV/dec [17].…”

“…Such device structure avoids the trouble of making individual bottom electrode, but has large parasitic effects and is unsuitable for radio frequency (RF) devices. Based on InAs NWs arrays, VGAA FETs have been fabricated by Lund's group [5,16,18] and RF characteristics with a cutoff frequency of f t =103 GHz and a maximum frequency of f max =155 GHz have been achieved through finger contacts [6]. In these InAs NW VGAA FETs, the bottom electrode is the patterned heavily doped InAs layer and a low-k material layer is added between the gate and the bottom electrodes.…”