High-performance ternary logic gates for nanoelectronics

Moaiyeri, Mohammad Hossein; Shamohammadi, Mohsen; Sharifi, Fazel; Navi, Keivan

doi:10.1504/ijhpsa.2015.072850

Cited by 6 publications

(6 citation statements)

References 16 publications

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“…The first two logic styles produce the target outputs with very few transistors. The third competitor [17] follows the same concept as the second one does. However, it employs a modified voltage division structure to generate ternary AND (instead of NAND).…”

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

“…The second proposed ternary DDCVSL AND/NAND outperforms almost all of the other competitors in terms of speed and energy consumption. Except [17], where the modified voltage dividers lead to strong driving power, the proposed design is the fastest cell when considering the production of both AND and NAND output functions. The voltage dividers in [17] increase driving capability, but on the other hand, they intensify power dissipation.…”

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

“…This is against the primary goal of MVL, which aims to reduce intra-chip interconnections. Most of the recent ternary circuits are also based on the assumption that there is only one power source available [6][7][8][9][10][11][17][18][19][20][21][22]. Dynamic DCVSL (DDCVSL) is a popular high-speed combined logic family in binary logic.…”

Section: Introductionmentioning

confidence: 99%

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Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Azimi

Mirzaee

Navi

et al. 2020

IET Computers & Digital Techniques

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Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static-to-dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state-of-the-art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS-like, SDCVSL, and pseudo N-type, respectively, in terms of energy consumption.

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Section: Simulation Results and Comparisonsmentioning

confidence: 99%

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

See 1 more Smart Citation

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Azimi

Mirzaee

Navi

et al. 2020

IET Computers & Digital Techniques

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“…The three valued system endeavors a 63% (log2/log3) mitigation in system complexity in relative to the two valued number system. The fundamental gates used to implement the ternary logic are the positive ternary inverter (PTI), standard ternary inverter (STI), and the negative ternary inverter (NTI) [41][42][43].…”

Section: Cntfet and Its Suitability For Ternary Designmentioning

confidence: 99%

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed cell uses a low-power cell core and a stack of 2 CNTFETs to discharge the read bit line (RBL) to ground, unlike the previous SRAM designs which use read buffers or transmission gates (TG) to alter the voltage levels on the RBL. The proposed TSRAM cell has been simulated relentlessly, using the Stanford 32 nm CNTFET technology mode file with Synopsis HSPICE tool under various operating conditions. Unlike other designs, the cross-coupled ternary inverters used as the cell core in the proposed TSRAM show higher gain and steep curves in the transition region mitigating the static power of the cell. The simulation results exhibit improvements in performance parameters like power consumption, energy, noise margins, and reliability. At 0.9 V supply voltage, the proposed TSRAM cell offers 52.44% and 43.17% reduction in write and read static power, a PDP reduction of 35.29% in comparison, and a 36.36% improvement in SNM compared to best designs under investigation. Also, the proposed TSRAM design shows higher robustness compared to other designs.

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“…[9][10][11] A significantly large segment of modern systems on chips (SoCs) is occupied by Static Random Access Memories (SRAMs) for their higher speed and lower power consumption and recently several designs of CNTFET-based SRAM cell have been proposed in literature. [12][13][14][15][16] In this paper we present a comparison of CNTFET models through the design of a 6T SRAM cell based on CNTFET technology, in order to identify the one more easily implementable in simulation software for CAD applications. In particular we consider our CNTFET model 11 and the Stanford-Source Virtual Carbon Nanotube Field-Effect Transistor model (VS-CNFET), 17 using for this the version downloadable on website of Stanford University, which, up today, refers to the model published in Refs.…”

mentioning

confidence: 99%

A Comparison of CNTFET Models through the Design of a SRAM Cell

Marani

Perri

2016

ECS J. Solid State Sci. Technol.

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In this paper we present a comparison of CNTFET models through the design of a SRAM cell, in order to identify the one more easily implementable in simulation software. In particular we consider two models, the first, already proposed by us, and the Stanford-Source Virtual Carbon Nanotube Field-Effect Transistor model (VS-CNFET). The simulation results of the design of a SRAM cell structure in CNTFET technology, by using the two models, are shown highlighting the comparison in terms of performance, power dissipation and stability.

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High-performance ternary logic gates for nanoelectronics

Cited by 6 publications

References 16 publications

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

A Comparison of CNTFET Models through the Design of a SRAM Cell

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