High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction

Huang, Fon-Shan; Huang, Shi-Yu; Ker, Ji-Wei; Chen, Yung‐Chang

doi:10.1109/tcsvt.2011.2162760

Cited by 143 publications

(54 citation statements)

References 17 publications

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“…One of the most robust approaches is the Scale Invariant Feature Transform [31] that apart from detecting features proposes a descriptor that is invariant to scale, rotation and illumination. Fully implemented SIFT has a high computational cost, which has led to the proposal of its optimized variants [16,12], GPU [38], FPGA [9,39] and ASIC [14] designs.…”

Section: Related Workmentioning

confidence: 99%

FPGA-based module for SURF extraction

Krajník

Šváb

Pedre

et al. 2014

Machine Vision and Applications

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We present a complete hardware and software solution of an FPGA-based computer vision embedded module capable of carrying out SURF image features extraction algorithm. Aside from image analysis, the module embeds a Linux distribution that allows to run programs specifically tailored for particular applications. The module is based on a Virtex-5 FXT FPGA which features powerful configurable logic and an embedded PowerPC processor. We describe the module hardware as well as the custom FPGA image processing cores that implement the algorithm's most computationally expensive process, the interest point detection. The module's overall performance is evaluated and compared to CPU and GPU based solutions. Results show that the embedded module achieves comparable disctinctiveness to the SURF software implementation running in a standard CPU while being faster and consuming significantly less power and space. Thus, it allows to use the SURF algorithm in applications with power and spatial constraints, such as autonomous navigation of small mobile robots.

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Section: Related Workmentioning

confidence: 99%

FPGA-based module for SURF extraction

Krajník

Šváb

Pedre

et al. 2014

Machine Vision and Applications

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“…Also, since most interest point detectors rely on the generation of the Gaussian pyramid and the application of a differentiation operator to the generated scales, only SIFT realizations are covered; the conclusions drawn for SIFT apply to other algorithms. Out from the SIFT implementations addressed here, [43] - [45] correspond to FPGA implementations, while [46] and [47] correspond to custom chips. None of these implementations includes the sensing devices; in all cases images are provided by separate, external sensors.…”

Section: B Overview Of Feature Detectors Hardware Artmentioning

confidence: 99%

“…Reference [45] achieves video frame rate processing for VGA images by using a scheme similar to that in [11]; namely, by first splitting the image into what they call segments, and then applying pipelining within each segment.…”

Section: B Overview Of Feature Detectors Hardware Artmentioning

confidence: 99%

CMOS-3D Smart Imager Architectures for Feature Detection

Suarez

Brea

Fernández-Berni

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3D IC technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixedsignal domain. It embeds in-pixel Correlated Double Sampling (CDS), a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel ADC (Analog to Digital Conversion). This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian and DoG detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a Switched-Capacitor (SC) network in less than 50 µs, outperforming more conventional solutions.

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“…A pure hardware FPGA based hardware implementations, also working with VGA images at real time is presented in [20]. Two CMOS implementations are described in [21,22], which reach the same frame rate for VGA and HD1080 images respectively. Finally, in [23][24][25], three pure hardware FPGA implementations able to generate descriptors at a faster rate (above 50 fps) are described.…”

Section: Introductionmentioning

confidence: 99%

FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

Doménech‐Asensi

Ruiz‐Merino

Zapata

et al. 2017

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)

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Abstract-This paper describes a hardware proposal to speed up the process of image matching in stereo vision systems like those employed by autonomous mobile robots. This proposal combines a classical window-based matching approach with a previous stage, where key points are selected from each image of the stereo pair. In this first step the key point extraction method is based on the SIFT algorithm. Thus, in the second step, the window-based matching is only applied to the set of selected key points, instead of to the whole images. For images with a 1% of key points, this method speeds up the matching four orders of magnitude. This proposal is, on the one hand, a better parallelizable architecture than the original SIFT, and on the other, a faster technique than a full image windows matching approach. The architecture has been implemented on a lower power Virtex 6 FPGA and it achieves a image matching speed above 30 fps.

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High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction

Cited by 143 publications

References 17 publications

FPGA-based module for SURF extraction

FPGA-based module for SURF extraction

CMOS-3D Smart Imager Architectures for Feature Detection

FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

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