High performance hardware support for elliptic curve cryptography over general prime field

Javeed, Khalid; Wang, Xiaojun; Scott, Mike

doi:10.1016/j.micpro.2016.12.005

Cited by 52 publications

(55 citation statements)

References 21 publications

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“…The performance metrics of AT is decreased around 90% and throughput is increased around 294%. So, our design provide better results in terms of AT and throughput with respect to recent designs are Hossain et al [2], Javeed [3]- [4] and Mrabet et al [5].…”

Section: Results and Performance Analysismentioning

confidence: 66%

“…So, we used throughput rate parameter and area-delay product (AT) parameter for comparison purposes. Table II, gives the simulated results and performance from various papers presented by Hossain et al [2], Liu et al [3], Lee et al [4], Vliegen [5], Ghosh et al [6], McIvor et al [7], Daly et al [8] and Kudithi et al [9]. We can observe that the results from Hossain et al [2] and Kudithi [9] are better in terms of area and computation time when compared with other literature results.…”

Section: Results and Performance Analysismentioning

confidence: 78%

“…Javeed [3]- [4] designs has implemented using Virtex-6 FPGA. The throughput is improved around 68% to 75% and AT is decreased around 88% to 90% when compared with our design.…”

Section: Results and Performance Analysismentioning

confidence: 99%

“…One of the efficient algorithm Binary Inversion Algorithm to compute modular inversion, which is easier to implement RTL based hardware perspective and also more area-efficient with high-speed operation. The modular inversion/division algorithm for ECC over p F was developed by Hossain [1,2], Javeed [3]- [4], Mrabet [5], Kudithi [6], Liu [7], Lee [8], Vliegen [9], Ghosh [10], McIvor [11], and Daly [12][13]. Among these McIvor described different hardware architectures for modular inversion algorithm and remaining authors are used binary inversion algorithm or extended Euclidean algorithm.…”

Section: Literature Surveymentioning

confidence: 99%

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An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

Kudithi¹,

Sakthivel²

2019

IJITEE

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The modular inversion operation is an essential hardware design for computing speed when we use it in cryptography applications. Through this work, we present a FSM based design methodology to achieve speed, area and high-performance modular binary inversion algorithm over 256-bit prime field. The proposed architecture implemented using Xilinx Virtex-7 FPGA device, it achieves 37% reduction in area-delay product and 15% and 16% of improvement in speed and throughput respectively, when compared with existing designs. Also, ASIC based implementation is done using TSMC 65nm CMOS technology, the synthesis results achieved the maximum operating clock frequency is 833 MHz and throughput of 626Mbps, which makes it suitable for speed-critical cryptoapplications.

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Section: Results and Performance Analysismentioning

confidence: 66%

Section: Results and Performance Analysismentioning

confidence: 78%

“…Javeed [3]- [4] designs has implemented using Virtex-6 FPGA. The throughput is improved around 68% to 75% and AT is decreased around 88% to 90% when compared with our design.…”

Section: Results and Performance Analysismentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

See 2 more Smart Citations

An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

Kudithi¹,

Sakthivel²

2019

IJITEE

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“…Several hardware implementations of ECC have been reported in [ 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 53 ], where some authors aimed to minimize the area use while others tried to reduce the computation time. Achieving a higher processing speed with low-area use is technically challenging.…”

Section: Performance Comparisonmentioning

confidence: 99%

Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve

Islam

Hossain

Hasan

et al. 2020

Sensors

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With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

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A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

Shah

Javeed

Azmat

et al. 2018

Circuit Theory & Apps

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SummaryThis workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art.

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High performance hardware support for elliptic curve cryptography over general prime field

Cited by 52 publications

References 21 publications

An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve

A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

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