High performance folded cascode OTA using positive feedback and recycling structure

Akbari, Meysam; Biabanifard, Sadegh; Asadi, Shahrouz; Yagoub, M.C.E.

doi:10.1007/s10470-014-0464-0

Cited by 58 publications

(19 citation statements)

References 14 publications

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“…For conventional structures, the low‐voltage regime and technology advancements hamper the development of miniaturized amplifiers. In contrast, multistage amplifiers has been reported to possess excellent response regarding advancements of CMOS technology . We know that over the past years, because of technology advancements, the supply voltage has undergone major reduction without any significant intervention on threshold voltage.…”

Section: Introductionmentioning

confidence: 99%

“…In contrast, multistage amplifiers has been reported to possess excellent response regarding advancements of CMOS technology. [2][3][4][5][6][7][8][9] We know that over the past years, because of technology advancements, the supply voltage has undergone major reduction without any significant intervention on threshold voltage. So cascode structures are not compatible with low-supply voltages and submicron fabrication, while multistage structures provide high direct current (DC) gain easily.…”

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confidence: 99%

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A high‐performance CMOS four‐stage amplifier

Zanjani

Asiyabi

Biabanifard³

2019

Int J Numerical Modelling

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In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

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Section: Introductionmentioning

confidence: 99%

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confidence: 99%

A high‐performance CMOS four‐stage amplifier

Zanjani

Asiyabi

Biabanifard³

2019

Int J Numerical Modelling

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“…And ring oscillator is a circuit usually uses transistors without using passive elements [4]. The main reason of the tendency to design full transistor CMOS circuits is the ability of easy integration with absence of passive elements which reduces the die area [12][13][14][15][16][17][18][19][20]. The most significant feature of a ring oscillator is lower cost due to lower die area and design simplicity [1,4,5].…”

Section: Introductionmentioning

confidence: 99%

Combined skewed CMOS Ring Oscillator

Biabanifard¹,

Largani²,

Asadi³

2015

ECIJ

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“…With OPAMP based circuits, the accuracy of the circuit is very dependent of the open loop gain of the OPAMPs [14][15][16][17]. It is possible to compensate by using cascod devices, cascading several stages, compensation techniques [16] and so on.…”

Section: Introductionmentioning

confidence: 99%