High performance 0.2 μm CMOS with 25 Å gate oxide grown on nitrogen implanted Si substrates

Self Cite

We have found that nitrogen incorporation in the gate-oxide, by implantation into the Si, degrades the low field inversion mobility. Although submicron transistors fabricated using nitrogen implantation have been reported to show higher drive currents compared with "pure" oxides, we have measured about 20% degradation in large area transistors for a 2e14 cm 2 nitrogen implant. These measurements were done using nMOS transistors with thin gate-oxides ( 4 nm). Thickness determination was done by simulation fit to capacitance-voltage (C-V) measurements by including quantization and tunneling effects. We furthermore, observed that the decrease in the mobility has an increased sensitivity to the channel doping concentration.

Section: Introductioncontrasting

confidence: 86%

Reduced electron mobility due to nitrogen implant prior to the gate oxide growth

Kamgar¹,

Clemens²,

Ghetti³

et al. 2000

Self Cite

“…These additional observations might be linked to the explanation of the improved oxide thickness uniformity [5,6], the prevention of B penetration, and the improved nMOSFET noise level. Results on 0.2-m nMOSFET's and preliminary XPS data have been presented separately [7]. It is likely that thin gate oxides grown on N-implanted Si substrates will attract more investigation for the interests of device applications as well as for the understanding of their properties.…”

Section: Discussionmentioning

confidence: 99%

Preventing boron penetration through 25-/spl Aring/ gate oxides with nitrogen implant in the Si substrates

Liu¹,

Ma²,

Luftman³

et al. 1997

Self Cite

For gate oxides thinner than 40Å, conventional schemes of incorporating N in the oxides might become insufficient in stopping B penetration. By implanting N into the Si substrates with a sacrificial oxide layer, we have grown 25Å gate oxide and prevented B penetration in the presence of F after 90 min of 850 C and 10 s of 1050 C anneals. SIMS analyses surprisingly reveal a N peak formed within the thin oxide layer, while no N is left in the Si substrate beyond the oxide layer. In addition, no B is seen in the substrate, either. As a consequence, threshold voltage of pMOSFET's is shifted to a more negative value which agrees with calculations assuming no B penetration. Meanwhile, threshold voltage of nMOSFET's is not affected by the N implant, which confirms that B penetration is the only explanation for the pMOSFET data. Prevention of B peneitration also improves the short-channel effects for 0.25-m pMOSFET's, while no difference is seen in nMOSFET's with and without N implant.

“…The adjustment was performed by the implants of indium (1.2 × 10 cm 2 70 KeV) and boron (1 × 10 cm 2 35 KeV). A gate oxide of 2.7 nm with pre-implant [5] was grown at 800 C for 20 min. The poly-Si spacer was then formed by the deposition of 58 nm undoped poly-Si followed by RIE etchback.…”

Section: Fabricationmentioning

confidence: 99%

Sub-100 nm /spl Gamma/-gate MOSFETs with self-aligned drain extension formed by solid phase diffusion

Woo

2000

High performance 60 nm 0-gate n-MOSFET's have been fabricated. The very fine poly-Si gates were made using deposition and etchback of poly-Si to form a sidewall along the conductive poly-Si/PSG dummy stack. Due to the relatively wide dummy stack, the low gate resistance is independent of the actual gate length; this is especially essential for rf circuits as high gate resistance could severely degrade high frequency performance. The diffusion source, PSG layer underneath the poly-Si, allowed the formation of an ultra-shallow self-aligned drain extension by solid phase diffusion. Together with a steep retrograde channel using indium, good subthreshold characteristics as well as high current drive were obtained.