High-level synthesis of nonprogrammable hardware accelerators

Schreiber, Robert; Aditya, Shail; Rau, B. Ramakrishna; Kathail, Vinod; Mahlke, Scott; Abraham, Santosh G.; Snider, Greg

doi:10.1109/asap.2000.862383

Cited by 112 publications

(106 citation statements)

References 14 publications

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“…Consequently, the derivation of memory interfaces between processor arrays and external memory devices is gaining attention from the research community. First attempts for solving the data I/O were based on ad-hoc arbitrator mechanisms implemented in hardware and controlled by a host [9].…”

Section: Related Workmentioning

confidence: 99%

On an external memory scheme for processor arrays

Perez-Andrade

Torres-Huitzil

Cumplido

et al. 2013

IEICE Electron. Express

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Abstract:The problem of generating memory interfaces between loop-based accelerators and external memory is gaining the attention from the high-level synthesis research community. This paper presents an external memory system for inserting/extracting data to/from a loop-based accelerator derived by a high-level synthesis approach. The memory system is composed by four architectural cases which could occur during hardware synthesis. The memory system is based on a global asynchronous local synchronous approach and the use of dualport memory banks. FPGA-based implementation results show that the proposed memory system is technologically achievable and provides a high-bandwidth without introducing communication overhead.

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Section: Related Workmentioning

confidence: 99%

On an external memory scheme for processor arrays

Perez-Andrade

Torres-Huitzil

Cumplido

et al. 2013

IEICE Electron. Express

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“…The primary goal of C-to-silicon synthesis frameworks such as AutoESL [23], Impulse C [7], Synopsys Synphony/PICO [15], CHiMPS [14], and Altera C2H [11] is to reduce the effort that creating accelerators requires, by building them directly from a high-level language. To accelerate execution, these tools must either infer parallel execution from serial code or force the programmer to rewrite their code in a more explicitly parallel language or dialect [18].…”

Section: Icer Performance and Efficiencymentioning

confidence: 99%

Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems

Arora

Sampson

Goulding-Hotta

et al. 2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scale systems, and many large software systems contain relatively little code that is amenable to automatic, semi-automatic, or even manual parallelization. Whereas accelerator approaches have traditionally achieved energy benefits as a side effect from increasing performance via parallel execution, ICERs aim to achieve energy gains even on code with little exploitable parallelism.Traditional approaches to automatically generating accelerators from existing software rely on inferring parallel execution from serial code, so they face the same code analysis challenges as parallelizing compilers. In contrast, because the ICER approach targets energy rather than performance, it easily scales to large, irregular applications that are poor candidates for traditional acceleration. Our results show that, compared to a baseline system with soft processor cores, ICERs can reduce energy consumption by up to 9.5× for the code they target and 2.8× for whole applications.

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“…The PACT project [10] at Northwestern University performs C to hardware synthesis by taking power/performance trade off into account. The PICO project [11,12] performs static timing analysis to identify chain of operators to minimize number of cycles while maintaining cycle time constraints.…”

Section: Related Workmentioning

confidence: 99%

A Model for Hardware Realization of Kernel Loops

Liao

Wong

Mitra

2003

Field Programmable Logic and Application

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Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In this paper, we consider two important loop optimization techniques, namely loop unrolling and software pipelining that can impact the performance and cost of the synthesized hardware. We propose a novel model that accounts for various characteristics of a loop, including dependencies, parallelism and resource requirement, as well as certain high level constraints of the implementation platform. Using this model, we are able to deduce the optimal unroll factor and technique for achieving the best performance given a fixed resource budget. The model was verified using a compiler-based FPGA synthesis framework on a number of kernel loops. We believe that our model is general and applicable to other synthesis frameworks, and will help reduce the time for design space exploration.

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High-level synthesis of nonprogrammable hardware accelerators

Cited by 112 publications

References 14 publications

On an external memory scheme for processor arrays

On an external memory scheme for processor arrays

Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems

A Model for Hardware Realization of Kernel Loops

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