Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In this paper, we consider two important loop optimization techniques, namely loop unrolling and software pipelining that can impact the performance and cost of the synthesized hardware. We propose a novel model that accounts for various characteristics of a loop, including dependencies, parallelism and resource requirement, as well as certain high level constraints of the implementation platform. Using this model, we are able to deduce the optimal unroll factor and technique for achieving the best performance given a fixed resource budget. The model was verified using a compiler-based FPGA synthesis framework on a number of kernel loops. We believe that our model is general and applicable to other synthesis frameworks, and will help reduce the time for design space exploration.
The increasing density and speed of modem j e l d programmable gate arrays ofer the reconjgurable systems using them greater capability andJ7exibili!y, in particular for more complex computation. However, there remains a vely important problem of how to design on a more abstract level to manage the vast hardware resource and shorten the design time. This paper presents an approach to compile a system level description to hardware through a conventional so/hvare intermediate representation (IR) of a state-of-the-art optimizing compiler for Explicitly Parallel Insmction Computing (EPIC) processors. The front end compiles C progrms into an intermediate representation for an injnite resource EPIC processor. The intermediate representation contains all the information of confrolJ7ow graph of basic blocks. It is /i.m this intermediate representation that we have devised means to generate synthesizable Register Transfer level (RTL-level) Verilog description that can be mapped info the reconjgurable HWdevice. We will describe the details of the translation process and the performance on actual FPGA hardware.
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