A Model for Hardware Realization of Kernel Loops

Liao, Jirong; Wong, Weng-Fai; Mitra, Tulika

doi:10.1007/978-3-540-45234-8_33

Cited by 15 publications

(7 citation statements)

References 12 publications

(11 reference statements)

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“…Previous approaches in predicting the impact of loop unrolling include Liao et al [2003] and Cardoso and Diniz [2004]. In Liao et al [2003], the authors propose a model for the hardware realization of kernel loops.…”

Section: Background and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Optimal Loop Unrolling and Shifting for Reconfigurable Architectures

Dragomir

Stefanov

Bertels

2009

ACM Trans. Reconfigurable Technol. Syst.

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In this article, we present a new technique for optimizing loops that contain kernels mapped on a reconfigurable fabric. We assume the Molen machine organization as our framework. We propose combining loop unrolling with loop shifting, which is used to relocate the function calls contained in the loop body such that in every iteration of the transformed loop, software functions (running on GPP) execute in parallel with multiple instances of the kernel (running on FPGA). The algorithm computes the optimal unroll factor and determines the most appropriate transformation (which can be the combination of unrolling plus shifting or either of the two). This method is based on profiling information about the kernel's execution times on GPP and FPGA, memory transfers and area utilization. In the experimental part, we apply this method to several kernels from loop nests extracted from real-life applications (DCT and SAD from MPEG2 encoder, Quantizer from JPEG, and Sobel's Convolution) and perform an analysis of the results, comparing them with the theoretical maximum speedup by Amdahl's Law and showing when and how our transformations are beneficial.

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Section: Background and Related Workmentioning

confidence: 99%

“…In Liao et al [2003], the authors propose a model for the hardware realization of kernel loops. The compiler is used to extract certain key parameters of the analyzed loop.…”

Section: Background and Related Workmentioning

confidence: 99%

Optimal Loop Unrolling and Shifting for Reconfigurable Architectures

Dragomir

Stefanov

Bertels

2009

ACM Trans. Reconfigurable Technol. Syst.

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show abstract

“…A number of other papers have focused on the appropriate use of dependence analysis and loop optimizations, such as unrolling, pipelining, and vectorization in the context of hardware synthesis of loop-based accelerators [18], [21], [27], [38]. Our work emphasizes hyperblock formation and irregular control flow in the presence of loops, but could easily benefit from these analyses and transformations as well.…”

Section: Loop Acceleratorsmentioning

confidence: 99%

Introducing control-flow inclusion to support pipelining in custom instruction set extensions

Zuluaga

Kluter

Brisk

et al. 2009

2009 IEEE 7th Symposium on Application Specific Processors

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Abstract-Multi-cycle Instruction set extensions (ISE) can be pipelined in order to increase their throughput; however, typical program traces seldom contain consecutive calls to the same ISE that would allow this temporal parallelism. Often, there are intermittent calls to branch instructions, at a minimum, that prevent the pipelined execution of subsequent calls to the same ISE within a loop. What is needed is ISEs that cover an entire loop body, which can create a stream of repeated calls to the same ISE during program execution; this, in turn, permits the use of hardware pipelining. To address this concern, we introduce a new type of ISE that borrows ideas from zero-overhead loop instructions to permit pipelined execution of loops. To further expose instruction-level parallelism, the ISE supports loops whose bodies form hyperblocks, which are regions of program control flow that have multiple exits (including loop iterations and break points within loops). These ISEs broaden the scope of instructionlevel parallelism and obtain higher speed ups compared to traditional ISEs, primarily through pipelining, the exploitation of spatial parallelism, and reducing the overhead of control flow statements and branches.

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“…Several approaches ( [4], [5], [6], [7], [8], [9]) are focused on accelerating kernel loops in hardware. They use different loop transformations (unrolling, pipelining, etc) to exploit parallelism and speedup the kernel.…”

Section: Background and Related Workmentioning

confidence: 99%

Loop unrolling and shifting for reconfigurable architectures

Dragomir

Stefanov

Bertels

2008

2008 International Conference on Field Programmable Logic and Applications

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Loops are an important source of optimization. In this paper, we propose a new technique for optimizing loops that contain kernels mapped on a reconfigurable fabric. We assume the Molen machine organization and programming paradigm as our framework. The method we propose extends our previous work on loop unrolling for reconfigurable architectures by combining unrolling with shifting to relocate the function calls contained in the loop body such that in every iteration of the transformed loop, software functions (running on GPP) execute in parallel with multiple instances of the kernel (running on FPGA). The algorithm is based on profiling information about the kernel's execution times on GPP and FPGA, memory transfers and area utilization. In the experimental part, we apply this method to a loop nest extracted from MPEG2 encoder containing the DCT kernel. The achieved speedup is 19.65x over software execution and 1.8x over loop unrolling.

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A Model for Hardware Realization of Kernel Loops

Cited by 15 publications

References 12 publications

Optimal Loop Unrolling and Shifting for Reconfigurable Architectures

Optimal Loop Unrolling and Shifting for Reconfigurable Architectures

Introducing control-flow inclusion to support pipelining in custom instruction set extensions

Loop unrolling and shifting for reconfigurable architectures

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