Optimal Loop Unrolling and Shifting for Reconfigurable Architectures

Dragomir, Ozana Silvia; Stefanov, Todor; Bertels, Koen

doi:10.1145/1575779.1575785

Cited by 9 publications

(7 citation statements)

References 13 publications

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“…Loop unrolling, also known as loop unwinding, is a well-known compiler optimization that can lead to signi cant performance improvements [23] . The effects of loop unrolling on CPU programs have been understood and described extensively in past work [24,25,26] . A typical 1X1 Loop unrolling and 2X1 Loop unrolling instruction execution sequence is illustrated in Fig.…”

Section: Loop Unrolling Mechanismmentioning

confidence: 99%

Minimizing control dependencies of pipelining through optimizing branch selection

Gao,

Shao

2024

Preprint

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In modern computer systems, processors achieve high performance through pipelining. Therefore, the execution efficiency of the pipelining is one of the critical factors impacting processor performance. The main factors that impact pipelining efficiency are data hazards caused by data dependencies and control hazards caused by control dependencies. Regarding the control hazards present in pipelining, although a few technologies are mentioned in the literature for addressing them, they frequently require significantly high latency and may not guarantee optimal quality. This paper introduces the Functional Function (FF), derived from the Fork function; by selectively executing branch instructions based on previous calculation results, the Functional Function can minimize control dependencies in pipelining and enhance the utilization of the processor pipelining via optimizing branch selection. The Intel VTune Profiler program analyzer was employed for data collection and analysis during the experiment to facilitate an unbiased comparison with existing methods. The experimental results indicate that the Functional Function significantly outperforms the existing methods, primarily reflected in the Pipeline utilization rate, CPI rate, and Bad Speculation rate. Furthermore, the utilization of the pipelining is enhanced by approximately 20%, accompanied by a nearly 1.5% increase in branch prediction accuracy compared with existing methods.

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Section: Loop Unrolling Mechanismmentioning

confidence: 99%

Minimizing control dependencies of pipelining through optimizing branch selection

Gao,

Shao

2024

Preprint

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“…Loop division on multiple smaller loops is proved to be appropriate when using performance aware devices such as FPGAs [27]. Since the loop unrolling method is not the only one, Dragomir et al [28] propose a combined technique (loop unrolling and loop shifting) in order to relocate the function calls for kernel based reconfigurable FPGAs.…”

Section: Loop Unrolling In Hardware Solutionsmentioning

confidence: 99%

The performance impact analysis of loop unrolling

Velkoski¹,

Gušev

Ristov

2014

2014 37th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO)

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Loop unrolling is a well known technique, which usually results with speedup of a program that contains loops. The effect is obtained by reducing the operations that require counter increases and branch jumps at the end of the loops.This paper analyzes the impact of loop unrolling on various processor types and memory patterns. The experiments show a high correlation between the cache and the problem size. The loop unrolling results with a higher speedup for the execution of a smaller size problem, while it does not have impact for a problem whose size is greater than the capacity of the last level cache size, due to the huge number of cache misses.Another important result is that the loop unrolling achieves greater speedup on Intel, rather than AMD CPU. In this paper we analyze and discuss the various behaviors of loop unrolling.

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“…The work in [9] focuses on simple kernel loops containing only one hardware kernel that would be accelerated on the FPGA and some software code that will always execute on the GPP. For this kind of loops, the authors proposed algorithms based on loop unrolling and loop shifting with the purpose of maximizing parallelization and performance.…”

Section: Motivationmentioning

confidence: 99%

“…In the case of loop shifting, only the first and the last kernels in the K-loop will execute concurrently with their pre-or post-software functions. It is proven in [9] that it is always beneficial to apply loop shifting wherever the data constraints allow it. This means that performance can be further improved if loop shifting is applied on smaller K-loops.…”

Section: Motivationmentioning

confidence: 99%

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Loop distribution for K-loops on Reconfigurable Architectures

Dragomir

Bertels

2011

2011 Design, Automation &Amp; Test in Europe

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Within the context of Reconfigurable Architectures, we define a kernel loop (K-loop) as a loop containing in the loop body one or more kernels mapped on the reconfigurable hardware. In this paper, we analyze how loop distribution can be used in the context of K-loops. We propose an algorithm for splitting K-loops that contain more than one kernel and intraiteration dependencies. The purpose is to create smaller loops (Ksub-loops) that have more speedup potential when parallelized. Making use of partial reconfigurability, the K-sub-loops can take advantage of having more area available for multiple kernel instances to execute in parallel on the FPGA. In order to study the potential for performance improvement of using the loop distribution on K-loops, we make use of a suite of randomly generated test cases. The results show an improvement of more than 40% over previously proposed methods in more than 60% of the cases. The algorithm is also validated with a K-loop extracted from the MJPEG application. A speedup of maximum 8.22 is achieved when mapping MJPEG on VirtexIIPro with partial reconfiguration and 13.41 when statically mapping it on the Virtex-4.

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Optimal Loop Unrolling and Shifting for Reconfigurable Architectures

Cited by 9 publications

References 13 publications

Minimizing control dependencies of pipelining through optimizing branch selection

Minimizing control dependencies of pipelining through optimizing branch selection

The performance impact analysis of loop unrolling

Loop distribution for K-loops on Reconfigurable Architectures

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